• Bulletin of the Korean Chemical Society
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• 제33권5호
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• pp.1653-1658
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• 2012

A new anthracene-containing conjugated molecule was synthesized through the Sonogashira coupling and reduction reactions. 1-Ethynyl-4-hexylbenzene was coupled to 2,6-bis((4-hexylphenyl) ethynyl)anthracene-9,10-dione through a reduction reaction to generate 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene. The semiconducting properties were evaluated in an organic thin film transistor (OTFT) and a single-crystal field-effect transistor (SC-FET). The OTFT showed a mobility of around 0.13 $cm^2\;V^{-1}\;s^{-1}$ ($I_{ON}/I_{OFF}$ > $10^6$), whereas the SC-FET showed a mobility of 1.00-1.35 $cm^2\;V^{-1}\;s^{-1}$, which is much higher than that of the OTFT. Owing to the high photoluminescence quantum yield of 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene, we could observe a significant increase in drain current under irradiation with visible light (${\lambda}$ = 538 nm, 12.5 ${\mu}W/cm^2$).

• 한국정보통신학회논문지
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• 제16권12호
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• pp.2741-2746
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• 2012

본 연구에서는 기존의 질화알루미늄갈륨/질화갈륨 이종접합 구조에서 강한 분극현상으로 인하여 구현하기 어려웠던 상시불통형 소자를 질화알루미늄갈륨 기판 혹은 버퍼층을 이용하여 구현하는 방법을 제안한다. 질화알루미늄갈륨 기판 혹은 버퍼층 위에 더 높은 Al 몰분율을 갖는 장벽층을 성장하고 최상부에 질화갈륨 층을 추가 성장하여 분극전하를 상쇄시키는 방법을 이용하여 선택적으로 게이트 아래의 채널만 공핍시켜 상시불통형 소자를 구현할 수 있다. 이를 통하여 본 연구에서는 상용 전력소자에서 요구하는 게이트 문턱전압 2 V 이상을 갖는 질화알루미늄갈륨 이종접합 전계효과 트랜지스터 에피구조를 제안한다.

• 전기전자학회논문지
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• 제17권4호
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• pp.531-536
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• 2013

The impact of UV irradiation process on the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor was investigated. Due to the high intensity UV irradiation before the gate dielectric deposition, the conductivity of AlGaN/GaN structure and the drain saturation current of the transistor increased by about 10 %. However, the pinch off characteristics of transistor was severely deformed by the process. By comparing the electrical characteristics of the transistors, it was proposed that the high intensity UV irradiation formed a sub-channel under the two dimensional electron gas of AlGaN/GaN structure even without additional impurity injection.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.635-640
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• 2016

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.659-660
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• 2007

• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1481-1486
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• 2013

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.