• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.141-157
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• 2001

Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.364-365
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• 2011

본 논문에서는 FeRAM을 주 기억장치 및 보조 기억장치로 활용하는 다중 채널 FeRAM 시스템을 설계한다. FeRAM 의 비 위발성과 저 전력 소모의 장점을 활용하는 한편 다중 채널을 이용한 병렬 처리와 FPGA 내부 버퍼를 사용을 통해 읽기/쓰기 속도를 향상시켰다[1].

• Proceedings of the Korean Ceranic Society Conference
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• 2003.10a
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• pp.200.1-200
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• 2003

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.649-658
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• 1997

Database management systems(DMBS)using bolatile memory shluld have a recovery function to protect data against system failutes.Recovery requires much overhead in transaction proessing and is one of the great factors that deteriorate the system performance.Recently, there have been a lot of studies on database systems with nonbolatile memory to enhance the performance.A nonbolatile memory called DFeRAM is one of the promising memory devices of the future technology, but this device does not support fine-franularity licking.In this paper, we present a dual plane FeRAM(DFeRAM)architecture to support the fine-granularity locking.We also propose a recovery algorithm for the database system with the DFeRAM based on a shadow paging methed.In order to analze the performance of the proposed algorithm, we present an analytical model and analyze the performance using the moedl.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.137-137
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• 2006

본 연구에서는 FeRAM 적용을 위한 BLT 캐패시터 제조시 CMP 공정압력 변화에 따른 Leakage Current의 특성에 대해서 연구하였다. 6-inch Pt/Ti/Si 웨이퍼를 사용하였으며, 기판 위에 졸-겔(Sol-Gel)법으로 모든 BLT를 스핀코팅을 이용하여 증착시켰다. 증착된 BLT는 $200^{\circ}C$에서 기본 열처리 후 다시 $700^{\circ}C$에서 후속 열처리 하였다. 이러한 과정을 두번 반복하였며, FeRAM 적용을 위한 BLT 캐패시터 제조시 CMP 공정 중 압력 변화를 달리하여 BLT 캐패시터를 제조한 후 Leakage Current를 측정하였다. 결과적으로 CMP 공정 시 압력의 증가에 따라 Leakage Current값이 증가하였다. CMP 공정시 압력과 박막 표면의 스크레치로 증가로 인해 Leakage Current의 증가하였다고 판단된다.

• Korean Journal of Materials Research
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• v.14 no.10
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• pp.688-695
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• 2004

The capacitor contact barrier(CCB) layers have been introduced in the FeRAM integration to prevent the Pt/Al reaction during the back-end processes. Therefore, the interdiffusion and intermetallic formation in $Pt(1500{\AA})/Al(3000{\AA})$ film stacks were investigated over the annealing temperature range of $100\sim500^{\circ}C$. The interdiffusion in Pt/Al interface started at $300^{\circ}C$ and the stack was completlely intermixed after annealing over $400^{\circ}C$ in nitrogen ambient for 1 hour. Both XRD and SBM analyses revealed that the Pt/Al interdiffusion formed a single phase of $RtAl_2$ intermetallic compound. On the other hand, in the presence of TiN($1000{\AA}$) barrier layer at the Pt/Al interface, the intermetallic formation was completely suppressed even after the annealing at $500^{\circ}C$. These were in good agreement with the predicted effect of the TiN diffusion barrier layer. But the conventional TiN CCB layer could not perfectly block the Pt/Al reaction during the back-end processes of the FeRAM integration with the maximum annealing temperature of $420^{\circ}C$. The difference in the TiN barrier properties could be explained by the voids generated on the Pt electrode surface during the integration. The voids were acted as the starting point of the Pt/Al reaction in real FeRAM structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.98-103
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• 2008

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.73-77
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• 2023

In this study, we developed a Multi-level FeRAM (Ferroelectrics random access memory) device utilizing different ferroelectric materials and analyzed its operation through C-V analysis using simulations. To achieve Multi-level operation, we proposed an MFM (Multi-Ferroelectric Material) structure by depositing two different ferroelectric materials with distinct properties horizontally on the same bottom electrode and subsequently adding a gate electrode on top. By analyzing C-V peaks based on the polarization phenomenon occurring under different voltage conditions for the two materials, we confirmed the feasibility of achieving Multi-level operation, where either one or both of the materials can be polarized. Furthermore, we validated the process for implementing the proposed structure using semiconductor fabrication through process simulations. These results signify the significance of the new structure as it allows storing multiple states in a single memory cell, thereby greatly enhancing memory integration.

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.43-43
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• 2000