• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.1138-1143
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• 2015

Effects of fabrication process variations on impedance of microelectrodes integrated on a neural probe were examined through equivalent circuit modeling and SPICE simulation. Process variation and the corresponding range were estimated based on experimental data. The modeling results illustrate that the process variation induced by metal etching process was the dominant factor in impedance variation. We also demonstrate that the effect of process variation is frequency dependent. Another process variation that was examined in this work was the thickness variation induced by deposition process. The modeling results indicate that the effect of thickness variation on impedance is negligible. This work provides a means to predict the variations in impedance values of microelectrodes on neural probe due to different process variations.

• 산업공학
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• 제16권3호
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• 대한전자공학회논문지
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• 제24권6호
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• pp.992-997
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• 1987

This paper describes the design and fabrication of an integrated circuit that can separate the horizontal SYNC., vertical SYNC. and composite SYNC. signal included in a composite video signal. The circuit that is based on the comparator level samplign method can separate a stable SYNC. signal even from an external circuit with large variation. It has been fabrivated by the SST bipolar process. Its chip size is 1.5x1.5mm\ulcorner As a result, we succeeded in fabrication of IC which satisfied DC characteristics and SYNC. singal separator function.

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.190-193
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• 2010

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

• 제어로봇시스템학회논문지
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• 제15권12호
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• pp.1240-1245
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• 2009

The throughput characteristics of the cluster tool with dual blade robot are analyzed. Using equipment's cycle time chart of the equipment, simple analytic form of the throughput is derived. Then, several important throughput characteristics are analyzed by the throughput formula. First, utilization of the process chamber and the robot are maximized by assigning the equipment to the process whose processing time is near the critical process time. Second, rule for selecting optimal number of process chambers is suggested. It is desirable to select a single process chamber plus a single robot structure for relatively short time process and multi process chambers plus a single robot, namely cluster tool for relatively long time process. Third, throughput variation between equipments due to the wafer transfer time variation is analyzed, especially for the process whose processing time is less than critical process time. And the throughput and the wafer transfer time of the equipments in our fabrication line are measured and compared to the analysis.

• 한국정밀공학회지
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• 제21권4호
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• pp.32-38
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• 2004

Laser-induced thermochemical wet etching of titanium in phosphoric acid has been investigated to examine the feasibility of this method fur fabrication of microstructures. Cutting, drilling, and milling of titanium foil were carried out while examining the influence of process parameters on etch width, etch depth, and edge straightness. Laser power, scanning speed of workpiece, and etchant concentration were chosen as major process parameters influencing on temperature distribution and reaction rate. Etch width increased almost linearly with laser power showing little dependence on scanning speed while etch depth showed wide variation with both laser power and scanning speed. A well-defined etch profile with good surface quality was obtained at high concentration condition. Fabrication of a hole, micro cantilever beam, and rectangular slot with dimension of tess than 100${\mu}{\textrm}{m}$ has been demonstrated.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 추계학술대회 논문집
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• pp.748-751
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• 2000

Microlens made by laser radiation method have advantages in the easiness of their fabrication. The process is based on the projection of a chromium-on-quartz reticle on to the Polymer using a pulsed 248nm KrF excimer laser. Fabrication process is a fluence-dependent rate and density. The lens shape is defined by a rotationally symmetric sluence distribution with smooth radial variation in the image plane of the reticle. A typical lens of 50㎛ diameter was fabricated by irradiating 2000 laser pulses within 40 seconds. The experimental results show microlens fabrication by UV laser is possible and well worth studying further.

• 대한전자공학회논문지
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• 제23권3호
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• pp.384-388
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• 1986

This paper describes the design and fabrication of an integrated circuit that can detect the teletext signal included in a composite video signal. The circuit that is based on the comparatorlevel sampling method can detect a stable data signal even from an external circuit with large variation. It has been fabricated by the SST bipolar standard process. Its chip size is $2.5x3.78mm^2$.

• 전기전자학회논문지
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• 제22권2호
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• pp.420-426
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• 2018

가까운 미래에, 전자의 ballastic 혹은 near-ballastic 이동이 가능한 CNT(Carbon NanoTube)를 활용한 CNTFET(Carbon NanoTube Field Effect Transistor)은 현재의 실리콘 기반 트랜지스터를 교체할 유력한 후보 중 하나로 고려되고 있다. 고성능의 CNTFET으로 대규모 집적회로를 구현하기 위해서는 semiconducting CNT가 CNTFET 안에 동일한 간격과 높은 밀도로 정렬되어 배치되어야 하지만, CNTFET 공정의 미성숙으로, CNTFET 안의 CNT는 불규칙하게 배치하게 되고, 현존하는 HSPICE 라이브러리 파일은 불규칙한 CNT 배치에 의한 성능의 변화를 회로 레벨에서 평가할 수 있는 기능을 지원하지 않는다. 이러한 성능의 변화를 평가하기 위해서 선형 프로그래밍을 활용한 방법이 과거에 제안되었으나, CNTFET의 전류와 게이트 커패시턴스를 계산하는 과정에서 오차가 발생할 수 있는 문제점이 있다. 본 논문에서는 언급한 오차가 발생되는 이유에 대해서 자세히 논하고, 이 오차를 줄일 수 있는 새로운 방법을 제시하고자 한다. 시뮬레이션 검토 결과, 새롭게 제시된 방법이 기존 방법의 오차, 7.096%를 3.15%까지 줄일 수 있음을 보이고 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.43-44
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• 2005

SU-8 is a epoxy based photoresist designed for MEMS applications, where a thick, chemically and thermally stable image is desired. But SU-8 has proven to be very sensitive to variation in processing variables and hence difficult to use in the fabrication of useful structures. In this paper, negative SU-8 photoresist processed has been characterized in terms of delamination. Based on a full factorial designed experiment. Employing the design of experiment (DOE), a process parameter is established, and analyzing of full factional design is generated to investigate degree of delamination associated with three process parameters: post exposure bake (PEB) temperature, PEB time, and exposure energy. These results identify acceptable ranges of the three process variables to avoid delamination of SU-8 film, which in turn might lead to potential defects in MEMS device fabrication.