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Statistical Analysis on Critical Dimension Variation for a Semiconductor Fabrication Process  

Park, Sung-Min (System LSI, Samsung Electronics Co., Ltd.)
Lee, Jeong-In (System LSI, Samsung Electronics Co., Ltd.)
Kim, Byeong-Yun (System LSI, Samsung Electronics Co., Ltd.)
Oh, Young-Sun (System LSI, Samsung Electronics Co., Ltd.)
Publication Information
IE interfaces / v.16, no.3, 2003 , pp. 344-351 More about this Journal
Abstract
Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.
Keywords
statistical analysis; variation; critical dimension; semiconductor;
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