• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.529-532
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• 2005

In this paper, we propose a motion picture processor for CSTN LCD. In order to eliminate flicker phenomenon, the proposed processor suggests a new driving scheme, SFP(Subgroup Frame Pattern). We use an input image compression methode from RGB(:8:8;8) to RGB(5:6:5) to improve quality of the image and apply the image to CSTN Module. The proposed hardware architecture has been implemented and verified using a FPGA on prototype board. The proposed Algorithm provide a lower computational complexity. Therefore the processor can be used in the display devices such as PDA, mobile phone and PMP(Portable Multimedia Player).

• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.5
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• pp.746-750
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• 2015

In this paper, we propose a simulator to evaluate the performance of the semi-active laser guidance or the quadrant photodetector and to simulate the laser power reflected from a target. The laser pulse repetition frequency was generated and synchronized with the laser pulse repetition(PRF) code. To evaluate the performances of the proposed methods, we implemented a prototype system and performed experiments. As a result, the generated high voltage was variable in the range of DC 3V to 340V and has the rate of change of 2000 V/s. PRF code can be generated within 50ms ∼ 100ms and the error is implemented within 0.3ns. The laser output is synchronized with the PRF code and has a dynamic range of 23.6dB.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.6
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• pp.11-17
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• 2001

Design and implementation of the MAC protocol processor prototype for high speed wireless LAN, which has interface with 5GHz OFDM PHY layer, is presented. We analyze the IEEE 802.11 MAC protocol specification and then separate the MAC protocol functions to be implemented by hardware and firmware and define the interface in which frames can be exchanged. That is, it is considered that high speed queue processing and interfaces with RISC processor and OFDM PHY layer. Protocol control and transmission/reception functions of the MAC functions are implemented in hardware in order to guarantee high speed processing in MAC layer. The developed MAC hardware block operates at 10MHz main clock. Therefore, transmission rate in PHY layer is about 80Mbps because data transmission/reception between MAC layer and PHY layer is performed as unit of octet. The designed FPGA MAC function chip has been implemented in wireless LAN test board and it is verified that DCF function is operated correctly.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.175-181
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• 2015

In this paper, we develop a 2.4GHz ISM band wireless communication platform prototype based on embedded linux which support can be u-Hospital service. The developed system is available connecting between ARM920T processor board and FPGA board and linking IEEE 802.11b PHY board, AD/DA(10Bit) and RF(2.4GHz) board for wireless access. It is also can be utilized for the embedded system design with IEEE 802.11b/g Access Point(Option: IEEE 802.11a/b/g) test due to the Embedded Linux. Also, the developed system is possible to test and verify the radio access technology, Modem(OFDM etc) and IP(Intellectual Property) circuit. And make the most use of the system, we search for a expansion to that home and mobile healthcare, wellness service application.

• Journal of Power Electronics
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• v.17 no.1
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• pp.56-66
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• 2017

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to "0" is detected as the faulty cell. Furthermore, consideration of generating the active cell pulses is completely described. Since the main advantage of this method is its simplicity, it can be easily implemented in a programmable digital device. Experimental results obtained with an 11-level inverter prototype confirm the effectiveness of the proposed fault detection technique. In addition, they show that the diagnosis method is unaffected by variations of the modulation index.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.228-238
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• 2002

This paper presents a digital controller of the electronic ballast using high frequency modulation method for the metal halide lamp. The proposed controller includes the control algorithm for soft starting, no load protection, over current protection and power control. The proposed digital controller, moreover, has the high frequency modulation scheme and the tracking algorithm to avoid acoustic resonance phenomena. For the math production with the low cost using the ASICs (Application Specific Integrated Circuit), the proposed digital controller has been designed with the FPGAs(Field Programmable Gate array) only, without any microprocessor. In this paper, the detail digital control algorithms are described and the experimental results of prototype 150w metal halide electronic ballast are presented.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.705-711
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• 2013

In this paper, we present a low-complexity non-coherent demodulation algorithm and hardware architecture for LR-WPAN systems which can support the variable data rate for various applications. The need for LR-WPAN systems that can support the variable data rate is increasing due to the emergence of various sensor applications. Since the existing symbol based double correlation (SBDC) algorithm requires the increase of complexity to support the variable data rate, we propose the sample based double correlation (SPDC) algorithm which can be implemented without the increase of complexity. The proposed non-coherent demodulator was designed by verilog HDL and implemented with FPGA prototype board.