• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.87-94
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• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2039-2044
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• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1370-1376
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• 2012

This paper proposes a gender recognition algorithm which classifies a male or female speaker. In this paper, characteristic vectors for the male and female speaker are analyzed, and recognition experiments for the proposed gender recognition by a neural network are performed using these characteristic vectors for the male and female. Input characteristic vectors of the proposed neural network are 10 LPC (Linear Predictive Coding) cepstrum coefficients, 12 LPC cepstrum coefficients, 12 FFT (Fast Fourier Transform) cepstrum coefficients and 1 RMS (Root Mean Square), and 12 LPC cepstrum coefficients and 8 FFT spectrum. The proposed neural network trained by 20-20-2 network are especially used in this experiment, using 12 LPC cepstrum coefficients and 8 FFT spectrum. From the experiment results, the average recognition rates obtained by the gender recognition algorithm is 99.8% for the male speaker and 96.5% for the female speaker.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.48-53
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• 2007

Some digital signal processing applications, such as FFT, request multiplications with a group(or, groups) of a few predetermined coefficients. In this paper, based on the modified CSD algorithm, an efficient multiplier design method for predetermined coefficient groups is proposed. In the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), and in the multiplier design used in 128 point $radix-2^4$ FFT, it is shown that the area, power and delay time can be reduced up to 34%.

• Journal of Korea Water Resources Association
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• v.38 no.10 s.159
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• pp.851-859
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• 2005

Normalized cross-correlation (correlation coefficient) is a useful measure for pattern matching in PIV (Particle Image Velocimetry) analysis. Because it does not have a corresponding simple expression in frequency domain, several fast but inexact measures have been used. Among them, three measures of correlation for PIV analysis and the normalized cross-correlation were evaluated with a sample calculation. The test revealed that all other proposed correlation measures sometimes show inaccurate results, except the normalized cross-correlation. However, correlation coefficient method has a weakpoint that it requires so long time for calculation. To overcome this shortcoming, a fast and exact method for calculating normalized cross-correlation is suggested. It adopts Fast Fourier Transform (FFT) for calculation of covariance and the successive-summing method for the denominator of correlation coefficient. The new algorithm showed that it is really fast and exact in calculating correlation coefficient.

• Journal of IKEEE
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• v.16 no.3
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• pp.189-196
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• 2012

This paper proposes new phase error compensation method of RVDT encoder in the FFT domain. Phase errors are measured with a small combination of compensation resistors and the changes of first order coefficients of FFT for each resistor are obtained. It is found that the coefficient change is inversely proportional to the inserted resistor. The proposed method takes less time and the size of the table is smaller than previous time domain approaches. In addition, the location of the compensation resistor can be found through axis transformation of the coefficients. Finally, the peak-to-peak phase error was improved to 0.57 which is two times better than previous one.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2093-2099
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• 2011

Speech signal and car noise signal such as muffler noise are segregated from the one which has both signals mixed using statistical method. To classify speech signal from the other in segregated signals, FFT coefficients were obtained for all segments of a signal where each segment consists of 128 elements of a signal. For several coefficients of FFT corresponding to the low frequencies of a signal, autocovariances are calculated between coefficients of same order of all segments of a signal. Then they were averaged over autocovariances. Linear equation was eatablished for the those autocovariances using the linear regression method for each siganl. The coefficient of the slope of the line gives reference to compare and decide what the speech signal is. It is what this paper proposes. The results show it is very useful.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.157-164
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• 2009

An efficient pipeline MDC Radix-4 FFT structure is proposed in this paper. Every stages in pipeline FFT structure consists of delay' commutator and butterfly. Proposed butterflies in front and rear stages utilize CORDIC and Common Sub-expression Sharing(CSS) techniques, respectively. It is shown that proposed butterfly structure can reduce the number of adders through sharing common patterns of CSD type coefficients. The Verilog-HDL modeling and Synopsys logic synthesis results that the proposed structure show 48.2% cell area reduction in the complex multiplication part and 22.1% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structures. Consequently, the proposed FFT structure can be efficiently used in various OFDM systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.97-105
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• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.