• Journal of Digital Convergence
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• v.15 no.11
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• pp.231-243
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• 2017

This paper provides a review of the electrical sensing biosensors and examine research cases of biosensors based on clothing and textiels. A biosensor which can measure bio-signals is a device that senses the physical and chemical characteristics of biological materials by using biological sensing materials. Therefore, wellness wear that is closely integrated with the user's real life will play an important role in achieving U-Health. The biosensors' unique feature which can be differentiated from the existing sensors is it's using of selective reactions and binding of biological substances. The electrical sensing biosensors are very small in size due to the processing of electrical signals, which can be used to create ubiquitous. Therefore, it is necessary to study electrical sensing biosensors that are easy to miniaturize to develop wellness wear. This paper describes the electrical sensing biosensor (an electrochemical method nanowire/carbon nanotube FET method) in detail. Finally, the future direction of biosensors to be applied to wellness wear is suggested.

• Journal of Sensor Science and Technology
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• v.4 no.2
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• pp.7-13
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• 1995

A new FET type semiconductor pressure sensor (PSFET : pressure sensitive field effect transistor) was fabricated and its operational characteristics were investigated. A ZnO thin film as a piezoelectric layer, $5000{\AA}$ thick, was deposited on a gate oxide of FET by RF magnetron sputtering. The deposition conditions to obtain a c-axis poling structure were substrate temperature of $300^{\circ}C$, RF power of 140watt, and working pressure of 5mtorr in Ar ambience. The fabricated PSFET device showed good linearity and stability in the applied pressure range($1{\times}10^{5}\;Pa{\sim}4{\times}10^{5}\;Pa$).

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• Journal of Advanced Engineering and Technology
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• v.11 no.4
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• pp.267-271
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• 2018

A high-frequency therapy device with improved output by modifying a high-frequency stimulator was fabricated. The details of the design include generating part design, high-frequency transformer design, large output FET installation, DC voltage input part design and gate input driver design. Based on the real test using the pork meat, the temperature distributions according to the current electric transfer method, penetration depth, electrode diameter size were measured. In the CET method, the penetration depth was 0.5 cm and in the RET method, the penetration depth was 20 cm or more. In addition, it was confirmed that the temperature rise according to the penetration depth in the RET system was substantially constant, and the temperature rise was remarkable as the electrode diameter was small. As a result, it has been confirmed that the high frequency therapy device is highly affected by various conditions of the electrode.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.27-31
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• 1996

In this paper, The SSPA(Solid State Power Amplifier) is 100 watts amplifier which is used with C-Band Satellite communication Up-Link frequency, 5.875 ∼6.425 GHz. SSPA requires more output power than is available from a single GaAs FET with result it is necessary to combine the output of many device. To achieve a high power, it is important to make a good N-way power divider which has a small different phase, good combining efficiency and high power handling capability. The reliability of Power GaAs FET decrease with increasing junction temperature, power amplifier in general dissipate amount of power. It is important to provide them with a heatsink and a temperature compensation circuit to dispose of the unwanted heat. To compensate temperature, Using PIN diode attenuator, it is enable to get a precision gain control. The output power of the SSPA is more than 100 watt with which the TWTA (Traveling-Wave Tube Amplifier) can be replaced. Each stage was measured by the Network analyzer PH8510C, Power meter Booton 42BD, The gain is more than 53 dB, flatness is less than 1.5 dB.

• Transactions on Electrical and Electronic Materials
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• v.14 no.5
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.3
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• pp.48-54
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• 2004

We have developed a new experimental driving system in order to make an easier drive experiment of PDP. By using the system, we can design and simulate the timing of the pulse in computer environment. As a result of the designed timing, we are able to program at PLD(Programmable Logic Device) and control high-voltage FET switches. The new system can reduce the time of the pulse compared with the previous logic gate ICs that realizes switching logic through hardware. In addition, it is a much easier way of changing the timing of the pulse due to the change of the driving method. By using the developed driving system we experimented on two different things- First, the realization of ADS Driving Method that run commonly; Second, gray scale realization on the three electrodes AC PDP.