• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.9
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• pp.104-109
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• 2021

Tactile sensors and integrated circuits that detect external stimuli have been developed for use in various industries. Most tactile sensors have been developed using the MEMS(micro electro-mechanical systems) process in which metal electrodes and strain sensors are applied to a silicon substrate. However, tactile sensors made of highly brittle silicon lack flexibility and are prone to damage by external forces. Flexible tactile sensors based on polydimethylsiloxane and using a multi-walled carbon nano-tube mixture as a pressure-sensitive material are currently being developed as an alternative to overcome these limitations. In this study, a manufacturing process of pressure-sensitive materials with low initial electrical resistance is developed and applied to the fabrication of flexible tactile sensors. In addition, flexible tactile sensors are developed with pressure-sensitive materials dispensed on a substrate with flexible mechanical properties. Finally, a study is conducted on the change in electrical resistance of pressure-sensitive materials according to the modulus of elasticity of the substrate.

• Journal of Intelligence and Information Systems
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• v.15 no.4
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• pp.213-224
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• 2009

This paper describes a real-time scheduling system re-construction project for automated manufacturing at a 300mm wafer fab of Korean semiconductor manufacturing company. During executing this project, for each main operation such as clean, diffusion, deposition, photolithography, and metallization, each adopted scheduling algorithm was developed, and then those were implemented in a real-time scheduling system. In this paper, we focus on the scheduling algorithms and real-time scheduling system for clean and diffusion operations, that is, a serial-process block with the constraint of limited queue time and batch processors. After this project was completed, the automated manufacturing utilizations of clean and diffusion operations became around 91% and 83% respectively, which were about 50% and 10% at the beginning of this project. The automated manufacturing system reduces direct operating costs, increased throughput on the equipments, and suggests continuous and uninterrupted processings.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.262-262
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• 2010

To investigate the effect of the amount of hydrogen on CVD grown-graphene, the flow rate of hydrogen was changed, while other process parameters were kept constant during CVD synthesis. Substrate which consists of 300nm-nickel/$SiO_2$/Si substrate, and methane gas mixed with hydrogen and argon were used for CVD growth. Graphene was synthesized at $950^{\circ}C$. The thickness and the defect of graphene were analyzed using raman spectroscopy. The synthesized graphene shows non-uniform and more defective below a certain amount of hydrogen.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.10a
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• pp.603-606
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• 2004

본 연구는 반도체 검사공정 중의 하나인 MBT 공정의 Rework 투입정책에 관한 연구이다. MBT 공정에서는 제품의 신뢰성과는 상관없이 설비오류로 인한 불량품이 다량으로 발생한다. 이러한 불량품을 MBT 공정의 재검사 작업인 Rework을 통해 양품으로 전환하게 된다. MBT 공정의 Rework은 FAB 공정 이후의 많은 공정을 거치지 않고 단일공정 진행으로 새로운 양품을 얻을 수 있는 이점을 가진다. 반면에 Rework 비용 및 공정재고비용이 발생하는 특징이 있다. 현재 MBT 공정의 Rework 작업은 정해진 규칙 없이 작업자 경험에 의존하여 진행하며, 제품의 중요도 및 재고량에 따라 투입이 정해진다. 또한 주문 작업의 투입일정과 납기를 고려하지 않은 Rework 작업으로 인해 납기차질이 발생하기도 한다. 본 연구에서는 Rework 작업이 생산계획에 영향을 주지 않는 범위 안에서의 투입계획을 제안한다. 또한 MBT 공정의 Rework 이익인 제조원가 절감이익과 비용인 Rework 비용, 재고비용을 고려한 Rework 제품 투입정책을 제안한다.

• Food Science and Preservation
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• v.15 no.5
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• pp.617-621
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• 2008

Sequential passes through $Sephadex^{TM}$ columns were used to select phages that displays ligands for dextran ($\alpha$-1,6 linked linear chains) from a phage antibody library. Those phages that bound to the $Sephadex^{TM}$ in each iteration were replicated in E. coli. A phage preparation isolated on the third round selection produced 5.4 nephelos turbidity units (NTU) in a dextran specific immunonephelometric assay, a 2.2 fold higher value than the phage preparation from the first round selection. This phage gave $72\;{\pm}\;10$ normalized intensity (N.I.) in a dip-stick assay against high molecular size dextran (T2000, $2\;{\times}\;10^6) and significantly lower color ($30\;{\pm}\;6$ N.I.) against low molecular size dextran (T10, $10^4$). The presence of an Fab insert in each of these phages was confirmed using a $\beta-galactosidase linked assay and polymerase chain reaction.

• Journal of Korean Institute of Industrial Engineers
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• v.40 no.3
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• pp.257-266
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• 2014

The semiconductor manufacturing industry is managed by a number of parameters from the FAB which is the initial step of production to package test which is the final step of production. Various methods for prediction for the quality and yield are required to reduce the production costs caused by a complicated manufacturing process. In order to increase the accuracy of quality prediction, we have to extract the significant features from the large amount of data. In this study, we propose the method for extracting feature from the cell level data of probe test process using OPTICS which is one of the density-based clustering to improve the prediction accuracy of the quality of the assembled chips that will be placed in a package test. Two features extracted by using OPTICS are used as input variables of quality prediction model because of having position information of the cell defect. The package test progress for chips classified to the correct quality grade by performing the improved prediction method is expected to bring the effect of reducing production costs.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.45-50
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• 2020

We investigated the Si_1-xGe_x surface properties when dry cleaning the films using NF₃ / H₂O remote plasma. After the dry cleaning process, it was found that about 80-250 nm wide bumps were formed on the SiGe surface regardless of Ge concentration in the rage of x = 0.1 ~ 0.3. In addition, effects of the dry cleaning processing parameters such as pressure, substrate temperature, and H₂O flow rates were examined. It was found that the surface bump is significantly dependent on the flow rate of H₂O. Based on these observations, we would like to provide additional guidelines for implementing the dry cleaning process to SiGe materials.