• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.362-365
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• 1999

This paper describes on thinning SDB SOI substrates by SDB technology and electrochemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic substrates were analyzed by using AFM and SEM, respectivelv.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.90-94
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• 1995

Reactive Ion Etching(RIE) of Si$_{3}$N$_{4}$ in a CF$_{4}$/O$_{2}$ gas plasma exhibits such good anisotropic etching properties that it is widely employed in current VLSI technology. However, the RIE process can cause serious damage to the silicon surface under the Si$_{3}$N$_{4}$ layer. When an atmospheric pressure chemical vapor deposited(APCVD) SiO$_{2}$ layer is used as a etch-stop material for Si$_{3}$N$_{4}$, it seems inevitable to get a good etch selectivity of Si$_{3}$N$_{4}$ with respect to SiO$_{2}$. Therefore, we have undertaken thorough study of the dependence of the etch rate of Si$_{3}$N$_{4}$ plasmas on $O_{2}$ dilution, RF power, and chamber pressure. The etch selectivity of Si$_{3}$N$_{4}$ with respect to SiO$_{2}$ has been obtained its value of 2.13 at the RF power of 150 W and the pressure of 110 mTorr in CF$_{4}$ gas plasma diluted with 25% $O_{2}$ by flow rate.

• Journal of Sensor Science and Technology
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• v.7 no.6
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• pp.426-431
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• 1998

This paper describes electrochemical etch-stop characteristics in THAH/IPA/pyrazine solution. I-V curves of n- and p-type Si in THAH/IPA/pyrazine solution were obtained. OCP(Open Circuit Potential) and PP (Passivation Potential) of p-type Si were -1.2 V and 0.1 V, and of n-type Si were -1.3 V and -0.2 V, respectively. Both n- and p-type Si, etching rates were abruptly decreased at potentials anodic to the PP. The etch-stop characteristics in THAH/IPA/pyrazine solution were observed. Since accurate etching stop occurs at pn junction, Si diaphragms having thickness of epi-layer were fabricated. Etching rate is highest at optimum etching condition, TMAH 25wt.%/IPA 17vol.%/pyrazine 0.1g/100ml. thus the elapsed time of etch-stop was reduced.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.54-59
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• 2002

This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• ETRI Journal
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• v.24 no.5
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• pp.398-400
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• 2002

Using $Cr_2O_3$ thin film, we developed a novel etch-stop technique for the protection of silicon surface morphology during deep ion coupled plasma etching of silica layers. With this technique we were able to etch a silica trench with a depth of over 20 ${\mu}m$ without any damage to the exposed silicon terrace surface. This technique should be well applicable to fabricating silica planar lightwave circuit platforms for opto-electronic hybrid integration.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.285-285
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• 2011

EUVL (Extreme Ultra Violet Lithography) is one of competitive lithographic technologies for sub-30nm fabrication of nano-scale Si devices that can possibly replace the conventional photolithography used to make today's microcircuits. Among the core EUVL technologies, mask fabrication is of considerable importance since the use of new reflective optics having a completely different configuration compared to those of conventional photolithography. Therefore new materials and new mask fabrication process are required for high performance EUVL mask fabrication. This study investigated the etching properties of SnO2 (Tin Oxide) as a new absorber material for EUVL binary mask. The EUVL mask structure used for etching is SnO2 (absorber layer) / Ru (capping / etch stop layer) / Mo-Si multilayer (reflective layer) / Si (substrate). Since the Ru etch stop layer should not be etched, infinitely high selectivity of SnO2 layer to Ru ESL is required. To obtain infinitely high etch selectivity and very low LER (line edge roughness) values, etch parameters of gas flow ratio, top electrode power, dc self - bias voltage (Vdc), and etch time were varied in inductively coupled Cl2/Ar plasmas. For certain process window, infinitely high etch selectivity of SnO2 to Ru ESL could be obtained by optimizing the process parameters. Etch characteristics were measured by on scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) analyses. Detailed mechanisms for ultra-high etch selectivity will be discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.57-63
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• 2008

In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio ($\tau_{sat}$) and increase of the thermal injection velocity ($V_{inj}$) contribute the increase of mobility. It is also shown that the decrease of the $\tau_{sat}$ is due to the decrease of the mean free path ($\lambda_O$). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased $V_{inj}$ because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.280-283
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.237.1-237.1
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• 2014

Etching is one of the most important steps in semiconductor manufacturing. In etch process control a critical task is to stop the etch process when the layer to be etched has been removed. If the etch process is allowed to continue beyond this time, the material gets over-etched and the lower layer is partially removed. On the other hand if the etch process is stopped too early, part of the layer to be etched still remains, called under-etched. Endpoint detection (EPD) is used to detect the most accurate time to stop the etch process in order to avoid over or under etch. The goal of this research is to develop a hardware and software system for EPD. The hardware consists of an Optical Plasma Monitor (OPM) sensor which is used to continuously monitor the plasma optical emission intensity during the etch process. The OPM software was developed to acquire and analyze the data to perform EPD. Our EPD algorithm is based on the following theory. As the etch process starts the plasma generated in the vacuum is added with the by-products from the etch reactions on the layer being etched. As the endpoint reaches and the layer gets completely removed the plasma constituents change gradually changing the optical intensity of the plasma. Although the change in optical intensity is not apparent, the difference in the plasma constituents when the endpoint has reached leaves a unique signature in the data gathered. Though not detectable in time domain, this signature could be obscured in the frequency spectrum of the data. By filtering and analysis of the changes in the frequency spectrum before and after the endpoint we could extract this signature. In order to do that, first, the EPD algorithm converts the time series signal into frequency domain. Next the noise in the frequency spectrum is removed to look for the useful frequency constituents of the data. Once these useful frequencies have been selected, they are monitored continuously in time and using a sub-algorithm the endpoint is detected when significant changes are observed in those signals. The experiment consisted of three kinds of etch processes; ashing, SiO2 on Si etch and metal on Si etch to develop and evaluate the EPD system.