• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 한국실내디자인학회논문집
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• 제20권1호
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• pp.80-88
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• 2011

Designs of Takashi Sugimoto suggested new concepts on the space after broking out fixed ideas, and attempted spatial expressions differently from existing interior decorations through independent thoughts and new interpretations. It is showing orientalism's influences strongly based on Japanese traditional beauty unlike western country's design trends. Takashi Sugimoto is implementing unique own design viewpoints by using materials in nature rather than artificial ones, and stressing extra ordinary view of the world having been edited with daily life through traditions and local cultures along with recycling old daily goods and wastes rather than pursuing modem and futuristic spatiality. Sugimoto thought that beautiful designs and uncommon ideas could be gotten from simple daily experiences, and thus materialized it with a technique of extraordinary daily life's implementation through such design viewpoints. Also, He pursues designs in which dense communications are made variously between spaces, space and user, and this becomes design techniques having been used mostly in his projects. It creates soft boundaries through using certain objet as an intermediate of doing communication or erasing physical boundaries, and then induces close communication within the space. This design viewpoints and techniques of Takashi Sugimoto have directed own discriminated designs nowadays.

• 전자공학회논문지
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• 제53권1호
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• pp.36-42
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• 2016

다중 셀 기반의 저장장치 특히, TLC 낸드 플래시는 낮은 가격을 무기로 SSD에 채용되고 있다. 그러나 TLC는 기존의 MLC대비 느린 성능과 내구성으로 인해 일부 블록(Block)을 SLC 영역으로 할당하여, 버퍼로 사용함으로써 성능을 개선하는 구조를 발전시켜 왔다. 본 논문에서는 SLC 버퍼 성능을 보다 향상시키기 위하여 SLC 블록에 대해 페이지 덮어쓰기 기능을 도입하였다. 이를 통해, 제한된 회수 이내에서 지움 동작 없이 데이터 갱신을 가능하도록 했다. 특히, 기존의 SLC 버퍼 영역이 채워지는 경우 유효 페이지를 TLC 블록으로 이동 복사하고, 해당 블록을 지워야 하는데, 제안된 방법을 통해 유효 페이지 복사 및 지움 동작을 50% 이상 줄일 수 있었다. 시뮬레이션 평가 결과 기존의 SLC 버퍼 대비 버퍼 덮어 쓰기를 통해 2배의 쓰기 성능 개선을 달성 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.133-133
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• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• 전기학회논문지
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• 제56권12호
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• 조명전기설비학회논문지
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• 제17권2호
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• pp.17-22
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• 2003

본 연구에서는 mP의 ADS 구동방식에서 초기화기간의 프라이밍 방전 특성에 대하여 실험적인 해석을 하였다. 방전에 의해 축적되는 벽전하의 총량과 벽전하가 축적되는 시간은 프라이밍 펄스의 폭과 무관하다. 또한 과잉 벽전하에 의한 자기소거 방전은 프라이밍 방전에 의한 벽전하량과 관계가 있으며 또한 프라이밍 방전에 의해 생성되는 공간전하와도 관계가 있다. 실험결과 프라이밍 펄스 폭은 8[$\mu\textrm{s}$], 전압은 163[V] 정도가 최적이다. 그리고 자기소거방전을 돕는 공간전하는 파라이밍 방전이 발생한 직후로부터 약 16[$\mu\textrm{s}$] 동안 존재한다. 그러므로 효과적인 초기화 과정을 위한 프라이밍 펄스의 폭은 16[$\mu\textrm{s}$] 이내가 적당하다.

• 한국융합학회논문지
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• 제11권7호
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• pp.73-78
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• 2020

현대 건축과 디자인은 확장적 사고로 타 장르와 융합하는 실험을 보여주고 있다. 본 연구는 건축의 비물질화와 비가시화 표현 수단으로서 그래픽 외피의 활용을 제안하는 데 의의를 둔다. '보이지 않는 건축'을 실현하는 방법은 크게 빛을 조작하는 소재를 이용하는 방법과 눈속임 기법을 바탕으로 하는 그래픽 접근으로 나눌 수 있다. 그중 서울광장 특설무대의 사례는 슈퍼그래픽을 활용해 건축물을 가볍고 투명하게 표현하고, 주변 환경에 방해되는 요소를 시야에서 사라지게 하는 방법을 보여준다. 장식의 수단을 넘어 효과적인 위장(僞裝) 기술로서 슈퍼그래픽 외피가 '보이지 않는 건축'의 시대의 유력한 표현 수단으로 활용되기를 기대한다.

• 대한한방내과학회지
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• 제43권3호
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• pp.344-362
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• 2022

Objective: In this study, the antioxidant activity of Ojayeonjong-hwan extracts was compared, and the following results were obtained. Methods: For hydrothermal and ethanol extracts, DPPH free radical and ABTS cationic radical erasing activity and reducing power using the FRAP method were compared, and the association between the antioxidant power of each extract and total phenol content was investigated. Significant results were obtained through in vitro apoptosis analysis through FFITC staining, mitochondrial membrane potential analysis, and ROS level measurement using C2C12 myoblastoma. Results: 1. In a comparison of DPPH free radical and ABTS cationic radical scavenging activity, water, and 70% ethanol extracts of Ojayeonjong-hwan (WEO and EEO) showed superior radical scavenging ability. 2. In the results of reducing power using the FRAP method, WEO and EEO showed antioxidant activity, which was shown to be dependent on the total phenol content contained in the extracts. 3. In comparison to the protective effect against H₂O₂-induced oxidative stress in C2C12 myoblasts, water extracts had no significant effect, but 70% ethanol extracts inhibited H₂O₂-mediated cytotoxicity in a concentration-dependent manner. 4. The cytotoxic protective effect of EEO against oxidative stress in C2C12 myoblasts was correlated with its inhibitory effects on H₂O₂-induced apoptosis and cell-cycle arrest. 5. In H₂O₂-treated C2C12 myoblasts, the apoptosis inhibitory effects of EEO were associated with the suppression of mitochondrial dysfunction and DNA damage. 6. The protective effects of EEO against H₂O₂-induced oxidative stress in C2C12 myoblasts were directly related to the inhibition of ROS generation. Conclusions: Ojayeonjong-hwan extracts all have protective potential against oxidative stress.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.175-178
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• 2008

플래시 메모리에서 읽기 작업은 속도도 빠르고 제약이 없으나 데이터 변경 시에는 덮어쓰기(overwrite)가 되지 않아 해당 데이터를 새로운 영역에 쓰고 이전에 존재하던 데이터는 무효 시켜야한다. 무효화시킨 데이터는 가비지컬렉션을 통해 지움 연산을 수행해야 한다. 지역 접근성을 가지는 데이터에 대해 가비지컬렉션을 통해 클리어 시킬 대상 목록을 선정할 때 cost-benefit 방법을 사용하면 성능은 좋으나 wear-leveling이 나빠지는 문제점이 있다. 본 연구에서는 wear-leveling을 개선하기 위해 플래시 메모리를 hot 데이터 그룹들과 cold 데이터 그룹들의 다수의 그룹으로 분할한 후 데이터를 배치하고 주기적으로 hot 데이터 영역과 cold 데이터 영역을 교체함으로써 wear-leveling과 성능을 개선하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.