• ETRI Journal
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• v.45 no.3
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of Information Display
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• v.2 no.4
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• pp.63-67
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• 2001

The switching power loss due to the panel capacitance during sustain period in AC PDP driving system can be minimized by using the energy recovery circuits. We proposed a new energy recovery circuit, SER1 (Seoul national univ. Energy Recovery circuit 1st). The experimental results of its application to a 42-inch surface discharge type AC PDP showed superior performance of SER1 in energy recovery efficiency and low distortion voltage waveform. Energy recovery efficiency of SER1 was measured up to 92.3 %, and the power dissipation during the sustain period was reduced by 15.2 W in 2000 pulse/frame compared with serial LC resonance energy recovery circuit.

• Journal of Power Electronics
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• v.7 no.4
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.319-325
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• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.341-352
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• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.204-207
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• 2003

This paper presents the electrical properties of PTFE (polytetrafluoroethylene) nozzle for circuit breaker. PTFE has been used widely as a nozzle material for circuit breaker. In the arcing environment in a circuit breaker, radiation is considered to be the major energy transport mechanism from the arc to the wall. The fraction of the radiation power is emitted out of the arc and reaches the nozzle wall, causing ablation at the surface and in the depth of the wall. The energy concentration in the material lead to the depolymerization and eventually lead to the generation of decomposed gas as well as some isolated carbon particles. The generation of the decomposed gas in the depth of the material causes inner explosion. The surface of nozzle becomes uneven. The flow of gas is not uniform due to the unevenness of the surface. Adding some fillers into PTFE is expected to be efficient for improving the endurability against radiation. In this experiment, three kinds of fillers that have endurance in the high temperature environment were added into PTFE. Dielectric constant, dissipation factor, electrical resistivity and dielectric strength of PTFE composites were investigated.

• Progress in Superconductivity and Cryogenics
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• v.23 no.2
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• pp.19-23
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• 2021

We have studied the breaking system that combines a resistive superconducting fault current limiter (SFCL) and a DC circuit breaker for DC fault current. To verify the design of the 15 kV DC SFCL, which was driven from the previous work, a 500 V DC system was built and a scale-down SFCL were manufactured. The manufactured SFCL module was designed as a bifilar coil which is a structure that minimizes inductive reactance. The manufactured SFCL module has been experiment to verify characteristics of the current-limiting performance in the DC 500 V system. Also, the manufactured FCL module was combined with the DC circuit breaker to be experimented to analyze the breaking performance. As a result of the experiment, when SFCL was combined to the DC circuit breaker, the energy dissipation received by the DC circuit breaker was reduced by up to 84% compared to when the DC circuit breaker operates alone. We are preparing methods and experiments for the optimal method for much higher performance as a future work.