• Title/Summary/Keyword: Embedded Capacitors

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Co-Silicide Device Characteristics in Embedded DRAM

  • Kim, Jong-Chae;Kim, Yeong-Cheol;Kim, Byung-Kook
    • Korean Journal of Crystallography
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    • v.12 no.3
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    • pp.162-165
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    • 2001
  • The EDL (Embedded DRAM and Logic) technologies with stack cell capacitors based on NO dielectric and Co-silicided source/drain junctions using a Ti capping material, were successfully implemented. The employed Co-silicided film exhibited junction leakage characteristics comparable to those of non-silicided junctions. Improved device characteristics without degradation of I/sub off/ was also achieved.

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Embedded Switched-Inductor Z-Source Inverters

  • Nguyen, Minh-Khai;Lim, Young-Cheol;Chang, Young-Hak;Moon, Chae-Joo
    • Journal of Power Electronics
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    • v.13 no.1
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    • pp.9-19
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    • 2013
  • In this paper, a ripple input current embedded switched-inductor Z-source inverter (rESL-ZSI) and a continuous input current embedded switched-inductor Z-source inverter (cESL-ZSI) are proposed by inserting two dc sources into the switched-inductor cells. The proposed inverters provide a high boost voltage inversion ability, a lower voltage stress across the active switching devices, a continuous input current and a reduced voltage stress on the capacitors. In addition, they can suppress the startup inrush current, which otherwise might destroy the devices. This paper presents the operating principles, analysis, and simulation results, and compares them to the conventional switched-inductor Z-source inverter. In order to verify the performance of the proposed converters, a laboratory prototype was constructed with 60 $V_{dc}$ input to test both configurations.

Design and Fabrication of Miniaturized LC Diplexer Embedded into Organic Substrate (적층 유기기판 내에 내장된 소형 LC 다이플렉서의 설계 및 제작)

  • Lee, Hwan-H.;Park, Jae-Y.;Lee, Han-S.
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.262-263
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    • 2007
  • In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

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Dielectric Properties of Polymer-ceramic Composites for Embedded Capacitors

  • Yoon, Jung-Rag;Han, Jeong-Woo;Lee, Kyung-Min
    • Transactions on Electrical and Electronic Materials
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    • v.10 no.4
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    • pp.116-120
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    • 2009
  • Ceramic-polymer composites have been investigated for their suitability as embedded capacitor materials because they combine the processing ability of polymers with the desired dielectric properties of ceramics. This paper discusses the dielectric properties of the ceramic ($BaTiO_3$)-polymer (Epoxy) composition as a function of ceramic particle size at a ceramic loading of 40 vol%. The dielectric constant of these ceramic-polymer composites increases as the powder size decreases. Results show that ceramic-polymer composites have a high dielectric constant associated with the $BaTiO_3$ powder with a 200 nm particle size, high insulation resistance, high breakdown voltage (> 22 KV/mm), and low dielectric loss (0.018-0.024) at 1 MHz.

High Security FeRAM-Based EPC C1G2 UHF (860 MHz-960 MHz) Passive RFID Tag Chip

  • Kang, Hee-Bok;Hong, Suk-Kyoung;Song, Yong-Wook;Sung, Man-Young;Choi, Bok-Gil;Chung, Jin-Yong;Lee, Jong-Wook
    • ETRI Journal
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    • v.30 no.6
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    • pp.826-832
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    • 2008
  • The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

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Characterization of Embedded Thick Film Capacitor in LTCC Substrate (유전체 Paste를 이용한 LTCC 내장형 후막 Capacitor 제작 및 평가)

  • Cho, Hyun-Min;Yoo, Myung-Jae;Park, Sung-Dae;Lee, Woo-Sung;Kang, Nam-Kee
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07b
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    • pp.760-763
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    • 2003
  • Low Temperature Cofired Ceramics (LTCC) technology is a promising technology to integrate many devices in a module by embedding passive components. For the module substrate, most LTCC structures have dielectric constants below 10 to reduce signal delay time. Some components, which need high dielectric constants, have not been yet embedded in LTCC module. So, embedding capacitor with high capacitance by applying another dielectrics with high dielectric constants in LTCC is an important issue to maximize circuit density in LTCC module. In this study, electrical properties of embedded capacitor fabricated by dielectric paste of high dielectric constants (K-100) and co-firing behavior with LTCC were investigated. To prevent camber development of co-fired structure, constrained sintering process was tested. Dielectric properties of embedded capacitors were calculated from their capacitance and impedance value. Temperature coefficient of capacitance were also measured.

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Statistical Modeling of 3-D Parallel-Plate Embedded Capacitors Using Monte Carlo Simulation

  • Yun, Il-Gu;Poddar, Ravi;Carastro, Lawrence;Brooke, Martin;May, Gary S.
    • ETRI Journal
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    • v.23 no.1
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    • pp.23-32
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    • 2001
  • Examination of the statistical variation of integrated passive components is crucial for designing and characterizing the performance of multichip module (MCM) substrates. In this paper, the statistical analysis of parallel plate capacitors with gridded plates manufactured in a multilayer low temperature cofired ceramic (LTCC) process is presented. A set of integrated capacitor structures is fabricated, and their scattering parameters are measured for a range of frequencies from 50 MHz to 5 GHz. Using optimized equivalent circuits obtained from HSPICE, mean and absolute deviation is calculated for each component of each device model. Monte Carlo Analysis for the capacitor structures is then performed using HSPICE. Using a comparison of the Monte Carlo results and measured data, it is determined that even a small number of sample structures, the statistical variation of the component values provides an accurate representation of the overall capacitor performance.

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Circuit Modeling of Interdigitated Capacitors Fabricated by High-K LTCC Sheets

  • Kim, Kil-Han;Ahn, Min-Su;Kang, Jung-Han;Yun, Il-Gu
    • ETRI Journal
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    • v.28 no.2
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    • pp.182-190
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    • 2006
  • The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.

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Highly Miniaturized and Performed UWB Bandpass Filter Embedded into PCB with SrTiO3 Composite Layer

  • Cheon, Seong-Jong;Park, Jun-Hwan;Park, Jae-Yeong
    • Journal of Electrical Engineering and Technology
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    • v.7 no.4
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    • pp.582-588
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    • 2012
  • In this paper, a highly miniaturized and performed UWB bandpass filter has been newly designed and implemented by embedding all the passive elements into a multi-layered PCB substrate with high dielectric $SrTiO_3$ composite film for 3.1 - 4.75 GHz compact UWB system applications. The high dielectric composite film was utilized to increase the capacitance densities and quality factors of capacitors embedded into the PCB. In order to reduce the size of the filter and avoid parasitic EM coupling between the embedded filter circuit elements, it was designed by using a $3^{rd}$ order Chebyshev circuit topology and a capacitive coupled transformation technology. Independent transmission zeros were also applied for improving the attenuation of the filter at the desired stopbands. The measured insertion and return losses in the passband were better than 1.68 and 12 dB, with a minimum value of 0.78 dB. The transmission zeros of the measured response were occurred at 2.2 and 5.15 GHz resulting in excellent suppressions of 31 and 20 dB at WLAN bands of 2.4 and 5.15 GHz, respectively. The size of the fabricated bandpass filter was $2.9{\times}2.8{\times}0.55(H)mm^3$.