• 한국재료학회지
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• 제29권2호
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• pp.106-115
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• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• 한국초전도ㆍ저온공학회논문지
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• 제10권1호
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• pp.15-18
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• 2008

To achieve high transport current without degradation under magnetic field, it is essential to artificially generate the pinning sites at which moving magnetic flux can be pinned. In this work, $ZrO_2$ nanodots were formed on the substrate surface using electro-spray deposition method. On top of the nanodots, the extended and effective pinning centers can be created. The positively charged Zr precursor solution was sprayed out from the needle using the corona discharge phenomena. Then, the sprayed precursor was deposited onto the negatively charged substrate surface followed by the heat treatment under the controlled atmosphere. Using the electrostatic force among the charged particles of precursor, evenly distributed and nano-sized dots were formed on the substrate surface. The size and density of the nanodots were studied by Atomic Force Microscopy. Also discussed are the effect of the deposition time and solution concentration on the size and density of the nanodot and processing variables in electro-spray method for the effective flux pinning centers in the superconducting films.

• 센서학회지
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• 제32권6호
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Transactions on Electrical and Electronic Materials
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• 제7권1호
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• 대한기계학회논문집B
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• 제27권10호
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• pp.1489-1497
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• 2003

Aerosol charge neutralizers with various radioactive sources have been used to apply an equilibrium charge distribution to aerosols of unknown charge distribution. However, the performance of aerosol charge neutralizers is not well known, especially for highly charged particles. Measurements of highly charged particles are needed in air cleaning devices, e.g. electrostatic precipitator, bag filter with a pre-charger, and electrical cyclone. In this study, the particle charging characteristics of two different aerosol charge neutralizers were experimentally investigated for singly charged monodisperse particles and highly charged polydisperse particles. One has radioactive source of $^{85}$ Kr (beta source, 2 mCi) and the other has $^{210}$ Po (alpha source, 0,5 mCi). The air flow rate passing through each aerosol charge neutralizer was changed from 0.2 to 2.5 L/min. The results show that the charge distribution of singly charged monodisperse particles passing through the $^{85}$ Kr aerosol charge neutralizer is well agreed with the Boltzmann equilibrium charge distribution at an air flow rate of 0.3 L/min, However, it deviates from the equilibrium charge distribution when the air flow rates are 0.6, 1,0, and 1,5 L/min, On the other hands, the effect of air flow rate is insignificant for the $^{210}$ Po aerosol charge neutralizer. The non-equilibrium character in charge distribution of highly charged polydisperse particles passing through the $^{85}$ Kr aerosol charge neutralizer greatly depends on the air flow rate, however it is insensitive to the air flow rate for the $^{210}$ Po aerosol charge neutralizer.

• 한국재료학회지
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• 제18권9호
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• pp.457-462
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• 2008

Through the electrostatic interaction between the poly-diallydimethylammonium chloride (PDDA) modified Multi-walled carbon nanotube (MWNT) and $SnO_2$ suspension in 1mM $NaNo_3$ solution, MWNT-$SnO_2$ nanocomposites (MSC) for anode electrodes of a Li-ion battery were successfully fabricated by colloidal heterocoagulation method. TEM observation showed that most of the $SnO_2$ nanoparticles were uniformly deposited on the outside surface of the MWNT. Galvanostatic charge/discharge cycling tests showed that MSC anodes exhibited higher specific capacities than bare MWNT and better cyclability than unsupported nano-$SnO_2$ anodes. Also, after 20 cycles, the MSC anode fabricated by heterocoagulation method showed more stable cycle properties than the simply mixed MSC anode. These improved electrochemical properties are attributed to the MWNT, which adsorbs the mechanical stress induced from volume change and increasing electrical conductivity of the MSC anode, and suppresses the aggregation between the $SnO_2$ nanoparticles.

• Transactions on Electrical and Electronic Materials
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• 제14권1호
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• pp.47-51
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• 2013

A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

• 전기전자학회논문지
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• 제18권1호
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• pp.25-30
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• 2014

본 논문에서는 파워 클램프에 적용하기 위한 SCR 기반의 ESD 보호회로를 제안하였다. 기존 SCR 구조의 낮은 홀딩 전압에 의한 래치-업 문제를 개선하기 위해 n+ 플로팅 영역을 삽입하고 추가적인 n-웰과 p-웰까지 확장된 p+ 캐소드 영역을 통해 높은 홀딩 전압을 가질 수 있도록 고안되었다. 제안된 ESD 보호회로는 높은 홀딩 전압을 통해 정상 동작 상태에서의 래치-업 면역 특성을 확보하였으며, 우수한 ESD 보호 능력을 가진다. 제안된 ESD 보호회로는 Synopsys사의 TCAD 시뮬레이션을 통해 전기적 특성을 검증하였다. 시뮬레이션 결과, 트리거 전압은 약 27.3 V에서 최대 32.71 V 사이에서 변화하는 반면, 홀딩 전압은 4.61 V에서 최대 8.75 V까지 상승하는 것을 확인하였다. 따라서 제안된 ESD 보호회로는 트리거 전압은 기존 SCR과 비슷한 수준을 유지하면서 높은 홀딩 전압을 갖는다.

• 한국환경농학회지
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• 제19권2호
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• pp.154-159
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• 2000

대기환경오염원인 오존을 벼와 콩에 처리하여 오존피해증상, 품종간 저항성 차이 및 유전양상을 밝히고자 가시피해, 피해엽율, 엽록소함량, 임실율 등을 조사한 결과를 요약하면 다음과 같다. 벼의 오존피해증상은 피해정도에 따라 잎에 작고 붉은 반점이 형성되거나 잎전체가 적갈색 또는 황백색으로 변색되며 잎끝부터 말리면서 고사하였다. 콩은 피해엽이 황백색 또는 흑갈색으로 변색되었으며 벼와 콩 모두 잎의 표면보다는 이면이, 신엽보다는 하위엽에서 뚜렷하게 나타났다. 벼의 오존저항성 정도는 밀양 23호와 농안벼가 저항성을, 추청벼가 감수성으로 조사되었다. 오존처리시간이 2시간에서 8시간으로 길어짐에 따라 벼의 피해엽율은 증가하였고 엽록소함량은 감소하는 경향이었지만 그 정도는 품종에 따라 다르게 나타났다. 콩의 품종별 오존저항성정도는 큰올콩과 단엽콩이 저항성을, 두유콩, 무한콩, 은하콩 및 푸른콩 등이 감수성으로 나타났다. 콩의 생육시기별 피해엽율은 품종에 따라 다소 다른 경향이었으나 대체로 파종후 45일 처리에서 피해엽율이 가장 높았다.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.31-36
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• 2011

본 논문은 0.13um CMOS 공정에서 적층출력드라이버 ESD 내성에 대하여 조사 하였다. 실제적인 I/O 시스템과 유사하게 프리-드라이버와 파워 클램프를 포함한 적층출력드라이버 회로를 구현하였다. 프리-드라이버 입력 연결 방법과 적층출력드라이버의 NMOS 크기에 따라 8가지 회로를 구성하였으며, TLP 실험을 통해서 HBM 내성을 조사하였다. 그 결과 프리-드라이버의 입력에 전원전압을 인가하고 적층출력드라이버는 가급적 유사한 크기로 진행한 조건이 다른 조건들 보다 높은 항복전류와 항복전압을 보여주었다. 이 테스트 결과를 토대로, 적층출력드라이버의 ESD 내성을 향상시킬 수 있는 설계 가이드를 제안하였다.