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A Study on ESD Robustness of Output Drivers for ESD Design Window Engineering  

Kim, Jung-Dong (School of Information & Communication Engineering, Sungkyunkwan University)
Lee, Gee-Du (School of Information & Communication Engineering, Sungkyunkwan University)
Choi, Yoon-Chul (School of Information & Communication Engineering, Sungkyunkwan University)
Kwon, Kee-Won (School of Information & Communication Engineering, Sungkyunkwan University)
Chun, Jung-Hoon (School of Information & Communication Engineering, Sungkyunkwan University)
Publication Information
Abstract
This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.
Keywords
ESD; Electrostatic discharge; HBM; TLP; staked drivers;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 T. Suzuki et al., "A study of ESD robustness of cascaded NMOS driver," Proc. of EOS/ ESDSymposium, pp. 403-407, 2007.
2 S. Cao, J.-H. Chun, E. Choi, S. Beebe, W. R. Anderson, R. W. Dutton, "Investigation on Output Driver with Stacked Devices for ESD Design Window Engineering," Proc. of EOS/ESD Symposium, pp. 1-8, 2010.
3 V. Vashchenko, A. Concannon, M. Beek, P. Hopper, "Physical Limitation of the Cascoded Snapback NMOS ESD Protection Capability Due to the Non-Uniform Turn-Off," IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 2, pp. 281-291, 2004.   DOI   ScienceOn
4 J.-H. Lee, J. R. Shih, Y. H. Wu, T. C. Ong, "The Failure Mechanism of High Voltage Tolerance IO Buffer under ESD," Proc. of International Reliability Physics Symposium, pp. 269-276, 2003
5 최진영, 송광섭, "HBM ESD 현상의 혼합모드 과도해석," 전자공학회논문지, 제 38권, SD편, 제1호, 1-12쪽, 2001년 1월
6 박재영, 송종규, "고전압 집적회로를 위한 래치업-프리 구조의 HBM 12kV ESD 보호회로," 전자공학회논문지, 제 46권, SD편, 제1호, 1-6쪽, 2009년 1월.
7 O. Semenov, H. Sarbishaei, M, Sachdev, "ESD Protection Device and Circuit Design for Advanced CMOS Technologies," Springer, 2008.
8 W. R. Anderson and D. B. Krakauer, "ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration," Proc. of EOS/ESD Symposium, pp. 54-62, 1998.
9 J. W. Miller, M. G. Khazhinsky, J. C. Weldon, "Engineering the cascaded NMOS Output buffer for maximum Vt1," Proc. of EOS/ESD Symposium, pp. 308-317, 2000.
10 S. Voldman, J. Never, S. Holmes, J. Adkisson, "Linewidth Control Effects on MOSFET ESD Robustness," Proc. of EOS/ESD Symposium, pp. 101-109, 1996.
11 K. Chatty, D. Alvarez, M. J. Abou-Khalil, C. Russ, J. Li and R. Gauthier, "Investigation of ESD performance of silicide-blocked stacked NMOSFETs in a 45nm bulk CMOS technology," Proc. of EOS/ESD Symposium, pp. 304-312, 2008.