Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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The SCR-based ESD Protection Circuit with High Latch-up Immunity for Power Clamp

파워 클램프용 래치-업 면역 특성을 갖는 SCR 기반 ESD 보호회로

  • Choi, Yong-Nam (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Han, Jung-Woo (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Nam, Jong-Ho (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Kwak, Jae-Chang (Dept. of Computer Science, Seokyeong University) ;
  • Koo, Yong-Seo (Dept. of Electronics and Electrical Engineering, Dankook University)
  • Received : 2013.12.12
  • Accepted : 2014.02.10
  • Published : 2014.03.31
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Abstract

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

본 논문에서는 파워 클램프에 적용하기 위한 SCR 기반의 ESD 보호회로를 제안하였다. 기존 SCR 구조의 낮은 홀딩 전압에 의한 래치-업 문제를 개선하기 위해 n+ 플로팅 영역을 삽입하고 추가적인 n-웰과 p-웰까지 확장된 p+ 캐소드 영역을 통해 높은 홀딩 전압을 가질 수 있도록 고안되었다. 제안된 ESD 보호회로는 높은 홀딩 전압을 통해 정상 동작 상태에서의 래치-업 면역 특성을 확보하였으며, 우수한 ESD 보호 능력을 가진다. 제안된 ESD 보호회로는 Synopsys사의 TCAD 시뮬레이션을 통해 전기적 특성을 검증하였다. 시뮬레이션 결과, 트리거 전압은 약 27.3 V에서 최대 32.71 V 사이에서 변화하는 반면, 홀딩 전압은 4.61 V에서 최대 8.75 V까지 상승하는 것을 확인하였다. 따라서 제안된 ESD 보호회로는 트리거 전압은 기존 SCR과 비슷한 수준을 유지하면서 높은 홀딩 전압을 갖는다.

Keywords

References

  1. Ming-Dou Ker, Cheng-Cheng Yen, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test", IEEE Journal of Solid-State Circuit, vol.43, no.11, pp. 2533-2545, November, 2008. https://doi.org/10.1109/JSSC.2008.2005451
  2. Albert Z. H. Wang, On-Chip ESD Protection for Integrated Circuits 2nd ed., Springer, US, 2002.
  3. O. Semenov, H. Sarbishaei, M, Sachdev, ESD Protection Device and Circuit Design for Advanced CMOS Technologies, Springer, Waterloo, 2008.
  4. Fred G. Kouper, "Design of SCR-based ESD Protection Considerations in Advanced High-Voltage Technologies for Automotive" in Proc. of the EOS/ESD Symp, pp. 54-63, September, 2006.
  5. Kui-Dong Kim, Jo-woon Lee, Sang-Jo Park, Yoon-sik Lee, Yong-Seo Koo, "A Study on the Novel SCR NANO ESD Protection Device Design and fabrication" in Proc. of the IKEEE, Vol.9, No.2, pp. 161-169, 2005.
  6. B. Keppens, Markus P. J. Mergence, Cong Son Trinh, Christian C. Russ, Bejamin Van Camp, Koen G. Verhaege, "ESD Protection Solutions for High Voltage Technologies" in Proc. EOS/ESD Symp., pp. 1-10, September, 2004.
  7. W. Y. Chen, M. D. Ker, Y. J. Huang, Y. N. Jou, and G. L. Lin, "Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration," Circuits and Systems, APCCAS, pp. 61-64, December, 2008.