• ETRI Journal
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• 제27권5호
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• pp.539-544
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• 2005

An analog CMOS vision chip for edge detection with power consumption below 20mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts; one is a logarithmic compression photocircuit, the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is OFF, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with $128{\times}128$ pixels, was below 20mW. The vision chip was designed using $0.25{\mu}m$ 1-poly 5-metal standard full custom CMOS process technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• 대한전자공학회논문지SD
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• 제47권8호
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• pp.47-55
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• 2010

본 논문에서는 고해상도 저전력 SAR 타입 ADC(아날로그 디지털 변환기)의 면적을 획기적으로 줄이기 위해서 역 다중화기 (Demultiplexer)와 카운터 (Counter)를 이용하는 타이밍 레지스터 (Timing register) 구조를 제안하였다. 전통적으로 사용되는 쉬프트 레지스터에 기반을 둔 타이밍 레지스터 구조는 해상도가 증가될수록 면적이 급격하게 증가하고, 또한 잡음의 원인이 되는 디지털 소비 전력도 증가되는 반면, 제안하는 구조는 해상도 증가에 따른 에러 보정 회로의 면적과 소비 전력 증가를 줄일 수 있다. 0.18 um CMOS 공정을 이용하여 제작하였으며, 제안한 타이밍 레지스터 구조를 이용하여, 기존 구조 대비 5.4배의 면적 감소와 디지털 전력 최소화의 효과를 얻을 수 있었다. 설계한 12 비트 SAR ADC는 11 비트의 유효 비트 (ENOB), 2 mW (기준전압 생성 블록 포함)의 소비전력과 1 MSPS의 변환 속도를 보였으며, 레이아웃 면적은 $1mm{\times}1mm$ 이었다.

• 한국전자파학회논문지
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• 제27권2호
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• pp.212-215
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• 2016

본 논문에서는 $0.18{\mu}m$ CMOS 공정을 사용하여 5.08 GHz에서 동작하는 링 전압 제어 발진기(Ring Voltage Controlled Oscillator, Ring VCO)를 제작하였다. Ring VCO는 3단 구조로 각 단의 트랜지스터 크기 비율을 다르게 하여 전류 변화에 따른 소모 전력이 달라짐을 확인하였다. Core의 양단 위, 아래에는 Current Mirror로 전류를 제어하도록 구성하였고, 주파수 조절을 위해 제어 전압을 추가하였다. Ring VCO 측정 결과, 주파수 범위는 65.5 %(1.88~5.45 GHz), 출력 전력 -0.30 dBm, 5.08 GHz 중심주파수에서 -87.50 dBc/Hz @1 MHz의 위상잡음을 갖는다. 또한, 2.4 V 전원에서 31.2 mW 소모 전력을 확인하였다.

• The Journal of Asian Finance, Economics and Business
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• 제8권3호
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• pp.1275-1286
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• 2021

The purpose of this study is to employ the theory of consumption value and consumers' innovative personality characteristics to explain the adoption of new personal electronics devices in Vietnamese market. This study adapts a quantitative survey-based approach to test hypotheses about relationship between consumption value, product specific innovativeness and new product adoption. The study uses a quantitative data set of 915 consumers who owned one mobile electronic device at least in Ho Chi Minh city, one of the biggest cities of Vietnam. The data was collected through personal interview and convenient sampling method. The conceptual model was tested using PLS structural equation model. The findings of this study suggest that both consumption value and product specific innovativeness influence the adoption of new electronic products. The results also reveal that product specific innovativeness mediates the relationship between consumption value and new product adoption. The study further identified that consumption value was taken as a second-order multidimensions construct with five components, namely functional value, epistemic value, economic value, social value and emotional value. As a result, the research suggests some implications to enhance marketers' capabilities to develop strategies for launching new hi-tech products in an emerging market as Vietnam.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.329-335
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• 2011

In this paper, a dual-band integer-N frequency divider is proposed for 2.4/5.2 GHz multi-standard wireless local area networks. It consists of a multi-modulus imbalance phase switching prescaler and two all-stage programmable counters. It is able to provide dual-band operation with high resolution while maintaining a low power consumption. This frequency divider is integrated with a 5 GHz VCO for multi-standard applications. Measurement results show that the VCO with frequency divider can work at 5.2 GHz with a total power consumption of 22 mW.

• 전자공학회논문지CI
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• 제47권1호
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• pp.30-40
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• 2010

IPTV 셋톱박스에서 가장 많이 사용하는 저장장치인 하드디스크는 가격에 비해 저장용량이 크고 입출력 속도가 빠르지만 스핀들 모터의 기계적 동작으로 인해 전력 소모가 많다는 단점이 있다. 셋톱박스에서 스트리밍 데이터를 재생하기 위하여 하드디스크의 스핀들 모터는 최대 전력을 사용하는 활성모드를 계속 유지해야 한다. 본 논문에서는 스트리밍 데이터 재생 시 전력 소모를 감소시키는 오프셋-버퍼링(Offset-Buffering)과 다중모드 스핀-다운(Multi Mode Spin-Down) 기법을 제안한다. 오프셋-버퍼링은 사용자의 시청 패턴을 분석하고 분석된 결과를 통해 버퍼링을 하므로 스핀들 모터의 모드를 대기모드로 길게 유지할 수 있다. 또한 오프셋 버퍼의 크기에 따라 다양한 모드로 스핀-다운을 하여 전력 소모를 줄일 수 있다. 실험 결과 본 논문에서 제안한 오프셋-버퍼링과 다중모드 스핀-다운은 기존의 풀-버퍼링(Full-Buffering)보다 28.3% 전력 소모량을 감소시켰으며, 스핀-업 횟수를 12.5% 줄였다.

• 대한전자공학회논문지SD
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• 제47권5호
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• pp.16-23
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• 2010

본 논문에서는 무선통신시스템의 수신단에 적용될 수 있는 6비트 250MS/s 플래쉬 A/D 변환기를 설계하였다. 제안하는 플래쉬 A/D 변환기는 기준 저항열에 입력전압범위 감지회로를 사용하여 비교기에서 소모하는 동적소비전력을 최소화 되게 설계하였다. 기존 플래시 A/D 변환기보다 아날로그단 소비전력은 4.3% 증가한 반면에, 디지털단 소비전력은 1/7로 감소하여 전체 소비전력은 1/2 정도로 감소하였다. 설계된 A/D 변환기는$0.18{\mu}m$ CMOS 1-poly 6-metal 공정으로 제작되었으며 측정 결과 입력 범위 0.8Vpp, 1.8V의 전원 전압에서 106mW의 전력소모를 나타내었다. 250MS/s의 변환속도와 30.27MHz의 입력주파수에서 4.1비트의 유효비트수를 나타내었다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권7호
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• pp.2496-2512
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• 2021

The requirements for powerful computing capability, high capacity, low latency and low energy consumption of emerging services, pose severe challenges to the fifth-generation (5G) network. As a promising paradigm, mobile edge networks can provide services in proximity to users by deploying computing components and cache at the edge, which can effectively decrease service delay. However, the coexistence of heterogeneous services and the sharing of limited resources lead to the competition between various services for multiple resources. This paper considers two typical heterogeneous services: computing services and content delivery services, in order to properly configure resources, it is crucial to develop an effective offloading and caching strategies. Considering the high energy consumption of 5G base stations, this paper considers the hybrid energy supply model of traditional power grid and green energy. Therefore, it is necessary to design a reasonable association mechanism which can allocate more service load to base stations rich in green energy to improve the utilization of green energy. This paper formed the joint optimization problem of computing offloading, caching and resource allocation for heterogeneous services with the objective of minimizing the on-grid power consumption under the constraints of limited resources and QoS guarantee. Since the joint optimization problem is a mixed integer nonlinear programming problem that is impossible to solve, this paper uses deep reinforcement learning method to learn the optimal strategy through a lot of training. Extensive simulation experiments show that compared with other schemes, the proposed scheme can allocate resources to heterogeneous service according to the green energy distribution which can effectively reduce the traditional energy consumption.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.257-263
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• 2002

Test scheduling of SoC becomes more important because it is one of the prime methods to minimize the testing time under limited power consumption of SoCs. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoCs is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position to minimize the idle test time of test resources.