• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1702-1708
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• 2013

OLED has good efficiency of power consumption by having no power consumption from black color as different with LCD. when it has white color, all RGB pixel should be glowing with high power consumption and that can make it has short life time. This paper suggest the way of low power consumption for OLED panel using adaptive luminance enhancement with color compensation and implement it as hardware. This way which is based on luminance information of input image makes converted luminance value from each pixel in real time. There is with using the basic idea of chromaticity reduction algorithm, showing new algorithm of color correction. And performance of proposed method was confirmed by comparing the conventional method in experiments about 48.43% current reduction. The proposed method was designed by Verilog HDL and was verified by using OpenCV and Windows Program.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2443-2450
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• 2014

In the motion recognition system using depth image, the depth image is converted to the real world formed 3D point cloud data for efficient algorithm apply. And then, output depth image is converted by the projective world after algorithm apply. However, when coordinate conversion, rounding error and data loss by applied algorithm are occurred. In this paper, when convert 3D point cloud data to depth image, we proposed efficient conversion method and its hardware implementation without rounding error and data loss according image size change. The proposed system make progress using the OpenCV and the window program, and we test a system using the Kinect in real time. In addition, designed using Verilog-HDL and verified through the Zynq-7000 FPGA Board of Xilinx.

• Journal of IKEEE
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• v.27 no.4
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• pp.683-686
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• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.

• ETRI Journal
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• v.30 no.1
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• pp.167-169
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• 2008

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode $1920{\times}1088$ 30 fps video in real time at a 30.8 MHz clock.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.177-180
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• 2000

This paper proposes the optimized hardware architecture for a high performance image downscaler The proposed downscaler uses non-linear digital filters for horizontal and vertical scalings. In order to achieve the optimization, the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The performance of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using the VHDL and implemented by using the IDEC-C632 0.65$\mu\textrm{m}$ cell library.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.465-472
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• 2017

Security has become one of the most important requirements for various devices for multi-sensor based embedded systems. The AES (Advanced Encryption Standard) algorithm is widely used for security, however, it requires high computing power. In order to reduce the CPU power for the data encryption of images, we propose a new image encryption module using hardware memoization, which can reuse previously generated data. However, as image pixel data are slightly different each other, the reuse rate of the simple memoization system is low. Therefore, we further apply an approximate concept to the memoization system to have a higher reuse rate by sacrificing quality. With the novel technique, the throughput can be highly improved by 23.98% with 14.88% energy savings with image quality loss minimization.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2005.11a
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• pp.413-416
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• 2005

본 본문에서는 여러 가지 카오스 방정식을 자율 이동 로봇에 내장할 수 있는 카오스 이동 로봇의 하드웨어를 구현하였다. 이 카오스 로봇은 로봇 주행이 다양한 곡면의 카오스 궤적을 가지고 주행 또는 탐색할 수 있도록 여러 종류의 카오스 회로 즉 Chua's 회로, Lorenz 회로, 하이퍼카오스 회로 등을 카오스 로봇에 내장하도록 설계되어 있도록 설계되어 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.60-67
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• 2015

This paper proposes an image-dependent color image enhancement method that uses adaptive luminance enhancement and color emphasis. It effectively enhances details of low-light regions while maintaining well-balanced luminance and color information. To compare the structure similarity and naturalness, we used the tone mapped image quality index (TMQI). The proposed method maintained better structure similarity in the enhanced image than did the space-variant luminance map (SVLM) method or the adaptive and integrated neighborhood dependent approach for nonlinear enhancement (AINDANE). The proposed method required the smallest computation time among the three algorithms. The proposed method can be easily implemented using the field-programmable gate array (FPGA), with low hardware resources and with better performance in terms of similarity.

• Proceedings of the KIEE Conference
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• 1997.07b
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• pp.724-727
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• 1997

This paper describes a control method of tank level using Fuzzy Inference Technique. In General, to control tank level without a dangerous overflow and with a high accuracy is difficult because of high order time delay and nonlinearity. None the less, the hardware controller using 80586 Microprocessor with DT-2801 board in this paper was successfully implemented, through a series of simulations and experiments, the superiority of the proposed fuzzy controller ta a conventional PID one was investigated.