• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.31-36
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• 2011

This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.40-50
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• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.

• Journal of IKEEE
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• v.20 no.3
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• pp.295-298
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• 2016

In this paper, we analysed the properties of the conventional ESD protection devices such as SCR, MVSCR, LVTSCR. The electrical characteristics and the turn-on time properties are simulated by Synopsys T-CAD simulator. As the results, the devices have the holding voltages between 2V and 3V, and the trigger voltage of about 20V with SCR, of about 12V with MVSCR, of about 9V with LVTSCR. The results of the simulation for the turn-on time properties are 2.8ns of SCR, 2.2ns of MVSCR, 2.0ns of LVTSCR. Thus, we prove that LVTSCR has the shortest turn-on time. However, the second breakdown currents(It2) of the devices are 7.7A of SCR, 5.5A of MVSCR, 4A of LVTSCR. This different properties have to be adapted by the operation voltages for I/O Clamps.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.2
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• pp.113-120
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• 2002

This paper describes characteristics of transient voltage waveforms caused by human electrostatic discharges(ESDs). For purpose of achieving the statistics on the meaningful amplitude and initial slope for transient ESD voltage waveforms, transient voltages due to human ESDs in various conditions were observed. A voltage measuring system with a wide bandwidth from DC to 400[MHz] was employed. ESD voltage waveforms are approximately the same as ESD current waveforms. Also the simulated results, which are calculated by the reposed equivalent circuit, are closely similar to the measured voltage waveforms. ESD voltage waveforms are strongly dependent on the approach speed and material of intruder, a fast approach causes ESD voltage waveform with a steep rise time than for a slow approach. The voltage waveforms from dialect finger ESDs have a relatively long rise time of 10∼30[ns], but their peaks are low. On the other side ESD voltage waveforms causer by screwdriver with insulating handle have a steep slope with a very short, less than 1[ns] rise time, but their initial spikes are extremely high The obtained results in this work would be applied to solve ESD problems for low voltage and small current electronic devices.

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.21-26
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• 2016

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different implant of channel blocking region was discussed for high voltage I/O applications. A conventional NSCR standard device shows low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified channel blocking structure demonstrate the improved ESD protection performance as a function of channel implant variation. Therefore, the channel blocking implant was a important parameter. Since the modified device with CPS_PDr+HNF structure satisfied the design window, we confirmed the applicable possibility as a ESD protection device for high voltage operating microchips.

• Journal of Ocean Engineering and Technology
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• v.35 no.4
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• pp.247-256
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• 2021

In order to minimize carbon emissions and greenhouse gas, the Energy Efficiency Design Index (EEDI) has become a major factor to be considered in recent years in a ship's design and operation phases. Energy-Saving Devices (ESDs) improve the EEDI of a vessel and make them environmentally friendly. In this research, the performance of an equalizing duct-type ESD installed upstream of a Korea Research Institute of Ships & Ocean Engineering (KRISO) Container Ship (KCS) model's propeller was investigated by computational fluid dynamics (CFD). Open-source CFD libraries, OpenFOAM, were used for computational analysis of the KCS with and without the ESD to verify the performance improvement. The flow field near the stern region and propulsive coefficients were considered for comparison. The results showed a considerable improvement when an ESD was used on the model. Using different sizes of the duct, the performance of the ESD was also compared. It was observed that with an increased duct size, the propulsive performance was improved.

• Journal of Gastric Cancer
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• v.23 no.3
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• pp.451-461
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• 2023

Purpose: Endoscopic submucosal dissection (ESD) is an effective treatment for early gastrointestinal neoplasms. However, this is a time-consuming procedure requiring various devices. This study aimed to evaluate the efficacy and safety of the ClearCut^TM Knife H-type, which is an integrated needle-tipped and insulated-tipped (IT) knife. Materials and Methods: Between July 2020 and September 2021, 99 patients with gastric epithelial neoplasms scheduled for ESD at three tertiary care hospitals were randomly assigned to H-knife (ClearCut^TM Knife H-type) or IT-knife (conventional IT knife) groups. Procedure times, therapeutic outcomes, and adverse events were analyzed. Results: A total of 98 patients (50 in the H-knife group and 48 in the IT-knife group) were analyzed. The median total procedure time was 11.9 minutes (range, 4.4-47.2 minutes) in the H-knife group and 12.7 minutes (range, 5.2-137.7 minutes) in the IT-knife group (P=0.209). Unlike the IT-knife group, which required additional devices in all cases, no additional devices were used in the H-knife group (P<0.001). En-bloc resection was performed for all lesions in both groups. The incidence of adverse events was not significantly different between groups (4.0% in the H-knife group vs. 8.3% in the IT-knife group; P=0.431). Conclusions: The newly developed hybrid device, the ClearCut^TM Knife H-type, had comparable efficacy to the conventional IT knife for gastric ESD.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.4
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• pp.108-116
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• 2002

This paper presents the measurements and evaluation of voltage waveforms due to human electrostatic discharge(ESD). The principle of operation and design rule of a new device for measuring the ESD fast transient voltages with very fast rise time were described. Peak values and rise time of ESD voltages derived from a charged human body under a variety of experimental conditions were examined. The frequency bandwidth of the proposed voltage measuring system ranges from DC to 400[㎒]. The ESD voltage waveform is nearly equal to the ESD current waveform and the peak amplitude of ESD current waveform is roughly proportional to the ESD voltage in each experimental conditions. A rapid approach results in a discharge voltage with a faster initial rise time than for a slow approach. The voltages caused by direct finger ESDs have an initial slope with a relatively long, 10∼30[ns] rise time, but the amplitude is small. On the other hand, the voltages caused by direct hand/metal ESDs have a steep initial s1ope with 1 ∼3[ns] rise time, but an initial spike is very big. As a consequence, it was found that the ESD voltage and current waveforms strongly depend on the approach speed and material of intruder. These measurement results would be useful to design the ESD protective devices.

• Journal of Power Electronics
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• v.12 no.6
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• pp.947-953
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• 2012

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

• Journal of IKEEE
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• v.26 no.2
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• pp.196-204
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• 2022

Electrostatic discharge (ESD) protection devices of P-type embedded silicon-controlled rectifier (PESCR) structure were analyzed for high-voltage operating input/output (I/O) applications. Conventional PESCR standard device exhibits typical SCR characteristics with very low-snapback holding voltages, resulting in latch-up problems during normal operation. However, the modified device with the counter pocket source (CPS) surrounding N⁺ source region and partially formed P-well (PPW) structures proposed in this study could improve latch-up immunity by indicating high on-resistance and snapback holding voltage.