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ESD Failure Analysis of PMOS Transistors  

Lee, Kyoung-Su (School of Information and Communication Engineering, Sungkyunkwan University)
Jung, Go-Eun (School of Information and Communication Engineering, Sungkyunkwan University)
Kwon, Kee-Won (School of Information and Communication Engineering, Sungkyunkwan University)
Chun, Jung-Hoon (School of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.2, 2010 , pp. 40-50 More about this Journal
Abstract
The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.
Keywords
ESD; Electrostatic discharge; ESD protection; failure analysis; PMOSFET;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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