• Journal of IKEEE
• /
• v.15 no.2
• /
• pp.143-148
• /
• 2011

MOS (Metal-Oxide Semconductor) devices among the most sensistive of all semiconductors to radiation, in particular ionizing radiation, showing much change even after a relatively low dose. The necessity of a radiation dosimeter robust enough for the working environment has increased in the fields of aerospace, radio-therapy, atomic power plant facilities, and other places where radiation exists. The power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) has been tested for use as a gamma radiation dosimeter by measuring the variation of threshold voltage based on the quantity of dose, and a maximum total dose of 30 krad exposed to a $^{60}Co$ ${\gamma}$-radiation source, which is sensitive to environment parameters such as temperature. The gate oxide structures give the main influence on the changes in the electrical characteristics affected by irradiation. The variation of threshold voltage on the operating temperature has caused errors, and needs calibration. These effects can be overcome by adjusting gate oxide thickness and implanting impurity at the surface of well region in MOSFET.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.859-862
• /
• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.583-586
• /
• 2009

A 14.1" XGA (1024${\times}$768) LCD panel with Integrated Black Data Insertion (IBDI) has been world first developed successfully based on the integrated amorphous Silicon TFT gate driver which we previously introduced. The notable features compared with the conventional integrated a-Si TFT gate driver circuit are that the circuit consists of Dual buffer, Carry buffer structure, and Q-node cross charging for stable signal scanning characteristic and prevention of coupling between signal lines.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.972-973
• /
• 2007

Relationships between field effect mobility and grain size on pentacene thin-film transistors with $polyimide/SiO_2$ gate dielectrics have been studied. 6 kinds of polyimide were used as surface treatment gate dielectric layer. Grain size of the pentacene thin film were between 5 and $30\;{\mu}m$ and depended on the polyimide. The field effect mobility were also depended on the polyimide and the those values were from 0.027 to $0.69\;cm^2/(Vs)$. The field effect mobility tends to increase with increasing the grain size. Precursor type polyimide containing polyamic acid show better mobility of $0.69\;cm^2/(Vs)$ than soluble type polyimide. Bias stress characteristics in air are discussed in the basis of the grain size.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.10
• /
• pp.918-923
• /
• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• Journal of Power Electronics
• /
• v.12 no.6
• /
• pp.886-894
• /
• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.779-782
• /
• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.4
• /
• pp.756-762
• /
• 2009

This paper proposes a high efficient Dual Buck Inverter design with a zero voltage switching (ZVS) control technique. The ZVS control is realized by adding a feedback loop circuit which is implemented by simple RS latch and TTL gate. The used load was 200W -Ceramic Metal Halide Lamp. The experimental results show that the proposed Inverter system could avoid the acoustic resonance and achieve high efficiency by Zero Voltage Switching.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.3
• /
• pp.148-152
• /
• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.944-947
• /
• 2005

Highly stable gate driver circuit using a-Si TFT has been developed. The circuit has dual-pull down structure, in which bias stress to the TFTs is relieved by alternating applied voltage. The circuit has been successfully integrated in 4-in. QVGA and 14-in. XGA TFT-LCD with a normal a-Si process, which are stable for over 2,000 hours at $60^{\circ}C$. The enhancement of stability of the circuit is attributed to retarded degradation of pull-down TFTs by AC driving.