• 제목/요약/키워드: Dual gate

검색결과 187건 처리시간 0.034초

Design of Multi-time Programmable Memory for PMICs

  • Kim, Yoon-Kyu;Kim, Min-Sung;Park, Heon;Ha, Man-Yeong;Lee, Jung-Hwan;Ha, Pan-Bong;Kim, Young-Hee
    • ETRI Journal
    • /
    • 제37권6호
    • /
    • pp.1188-1198
    • /
    • 2015
  • In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

AC-3와 MPEG-2 오디오 공용 복호화기의 설계 (A design of dual AC-3 and MPEG-2 audio decoder)

  • 고우석;유선국;박성욱;정남훈;김준석;이근섭;윤대희
    • 한국통신학회논문지
    • /
    • 제23권6호
    • /
    • pp.1433-1442
    • /
    • 1998
  • The thesis presents a dual audio decoder which can decode both AC-3 and MPEG-2 bitstream. The MPEG-2 synthesis processi s optimized via FFT to establish the common data path with AC-'3s. A dual audio decoder consists of a DSP core which performs the control-intensive part of each algorithm and a common synthesis filter which perfomrs the computation-intensive part. All the components of the dual audio decoder have been described in VHDL and simulated with a SYNOPSYS tool. The software modeling of the DSP core was used for functional validation. After being synthesized using 0.6 .mu.m-3ML technology standard cell, the dual audio decoder was simulated at gate-level with a COMPASS tool for hardware validation.

  • PDF

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

  • Mohapatra, S.K.;Pradhan, K.P.;Sahu, P.K.
    • Transactions on Electrical and Electronic Materials
    • /
    • 제14권6호
    • /
    • pp.291-294
    • /
    • 2013
  • When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

A Novel Design of Low Noise On-panel TFT Gate Driver

  • Deng, Er Lang;Shiau, Miin Shyue;Huang, Nan Xiong;Liu, Don Gey
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
    • /
    • pp.1305-1308
    • /
    • 2008
  • In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.

  • PDF

1700 V급 EST소자의 설계 및 제작에 관한 연구 (Design and Fabrication of 1700 V Emitter Switched Thyristor)

  • 강이구;안병섭;남태진
    • 한국전기전자재료학회논문지
    • /
    • 제23권3호
    • /
    • pp.183-189
    • /
    • 2010
  • In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

비전도성 폐기물 용융처리를 위한 혼합형 플라즈마토치 시스템 특성 연구 (A Study on the Properties of the Dual-mode Plasma Torch System for Melting the Non-conductive Waste)

  • 문영표;최장영
    • 전기학회논문지
    • /
    • 제65권1호
    • /
    • pp.73-80
    • /
    • 2016
  • The preliminary test for the dual mode plasma torch system was carried out to explore the operation properties in advance. The dual mode plasma torch system that is able to operate in transferred, non-transferred, or dual mode is very adequate for melting the mixed wastes including nonconductive materials such as concrete, asbestos, etc. since it exploits both the high efficiency of heat transfer to the melt in transferred mode and stable operation in non-transferred mode. Also, system operation including restarting is reliable and very easy. A stationary melter with a refractory structure was designed and manufactured considering the melting behavior of slags to minimize the refractory erosion. The power supply for the dual mode plasma torch system built with high power insulated gate bipolar transistor (IGBT) modules has functions for both current control and voltage control and is sufficient to suppress the harmonics during the operation of the plasma torch. The power supply provides two different voltages for transferred operation and non-transferred. It is confirmed that the operation voltage in transferred is always higher than non-transferred. The dual mode plasma torch system was successfully developed and is under operation for a melting experiment to optimize operation data.

Dual-Gate MESFET를 이용한 분포형 주파수 혼합기의 설계 (Design of a Distributed Mixer Using Dual-Gate MESFET's)

  • 오양현;안정식;김한석;이종악
    • 전기전자학회논문지
    • /
    • 제2권1호
    • /
    • pp.15-23
    • /
    • 1998
  • 본 논문에서는 DGFET를 이용한 초고주파용 분포형 믹서가 연구되었다. 분포형 믹서 회로는 게이트, 드레인 전송선로와 입, 출력단에서 정합회로 및 DGFET들로 구성된다. RF와 LO신호가 각 게이트 전송선로의 입력 단에 인가되면, DGFET의 전달 컨덕턴스를 통해 드레인 전송선로로 전달되며, 각 드레인단의 출력된 신호들은 설계에 따라 동위상으로 더해지게 되고, 이러한 형태의 믹서는 변환이득을 개선할 수 있을 뿐만 아니라 각 소자의 임피던스가 전송선로에 흡수되므로 초광대역을 특성을 갖는다. 또한, 보다 높은 주파수까지 광대역 특성을 갖게 하기 위해서 각 전송선로의 입 출력 단에 m-유도 영상 임피던스 개념을 도입하여 입 출력 단을 정합 하였다, 이러한 분포형 믹서를 마이크로스트립 기판 위에 설계 및 제작하였고 광대역 특성 및 변환이득, RF/LO 분리도 등을 컴퓨터 시뮬레이션 및 실험을 통해 검증하였다.

  • PDF

이중대역 무선랜 응용을 위한 높은 격리도와 선형성을 갖는 MMIC SPDT 스위치 (High Isolation and Linearity MMIC SPDT Switch for Dual Band Wireless LAN Applications)

  • 이강호;구경헌
    • 대한전자공학회논문지TC
    • /
    • 제43권1호
    • /
    • pp.143-148
    • /
    • 2006
  • 본 논문에서는 이중대역 무선랜 응용을 위한 SPDT(single-pole double-throw) 스위치를 설계 및 제작하였다. 높은 격리도와 송신단의 선형성을 개선하기 위해 적층-게이트(stacked-gate)를 이용하는 비대칭구조를 제안하였다. 제안한 SPDT 스위치의 트랜지스터의 게이트-폭과 제어전압 그리고 적층-게이트의 개수는 모의실험을 통해 최적의 값으로 설계되었고, 500mS/mm의 Gmmax와 150GHz의 fmax를 갖는 $0.25{\mu}m$ GaAs pHEMT 공정을 이용하여 제작하였다. 설계된 스위치는 $DC\~6GHz$ 대역에서 0.9dB 이하의 삽입손실과 송신시 40dB 이상의 격리도와 수신시 25dB 이상의 격리도를 나타내었고, -3/0V 제어전압으로 23dBm의 입력 PldB 를 보였다. 제작된 SPDT 스위치는 $1.8mm{\times}1.8mm$의 면적을 갖는다.

Design Consideration of Bulk FinFETs with Locally-Separated-Channel Structures for Sub-50 nm DRAM Cell Transistors

  • Jung, Han-A-Reum;Park, Ki-Heung;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제8권2호
    • /
    • pp.156-163
    • /
    • 2008
  • We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

A Methodology of Dual Gate MOSFET Dosimeter with Compensated Temperature Sensitivity

  • Lho, Young-Hwan
    • 전기전자학회논문지
    • /
    • 제15권2호
    • /
    • pp.143-148
    • /
    • 2011
  • MOS (Metal-Oxide Semconductor) devices among the most sensistive of all semiconductors to radiation, in particular ionizing radiation, showing much change even after a relatively low dose. The necessity of a radiation dosimeter robust enough for the working environment has increased in the fields of aerospace, radio-therapy, atomic power plant facilities, and other places where radiation exists. The power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) has been tested for use as a gamma radiation dosimeter by measuring the variation of threshold voltage based on the quantity of dose, and a maximum total dose of 30 krad exposed to a $^{60}Co$ ${\gamma}$-radiation source, which is sensitive to environment parameters such as temperature. The gate oxide structures give the main influence on the changes in the electrical characteristics affected by irradiation. The variation of threshold voltage on the operating temperature has caused errors, and needs calibration. These effects can be overcome by adjusting gate oxide thickness and implanting impurity at the surface of well region in MOSFET.