• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of electromagnetic engineering and science
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• v.14 no.2
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• pp.68-73
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• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.719-725
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• 2019

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1817-1823
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• 2009

A design of cascaded distributed amplifier with a broadband amplification is described in this paper. A medium power device with 23dBm, max output power under the optimal narrow-band power matching condition is adopted for the design and fabrication of the cascaded distributed amplifier. In general, conventional distributed amplifiers with the parallel connected input ports have a low gain, and previous cascaded distributed amplifiers show a relatively low output power of 10dBm at most, which is the upper limit of small signal amplification. However, the cascaded distributed amplifier in this paper shows the gain of $18.15{\pm}0.75dB$ and output power of 20dBm over $300MHz{\sim}2GHz$ from the measurement, so it can be well adopted as a wideband driver amplifier.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.686-689
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• 2003

This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.161-161
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• 2010

In order to achieve low power consumption and the uniform power spectrum of LED BLU (Back Light Unit) system, new circuits with a 2 stage L-C (Inductor-Capacitor) coupler have been proposed. From the simulation results based on our proposed model, the ripple power of the L-C regulation-embedded BLU circuit shows a dramatic reduction by more than 89.3% as compared to the normal BLU (without L-C circuits). This indicates that the proposed circuit is very promising for the realization of high-efficiency BLU circuits.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.34-38
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• 2006

A low cost PDP sustain power supply is proposed based on flyback topology. By using Boundary Conduction Method(BCM) to control input current regulation, DCM condition can be met under all load conditions. Another feature of the proposed method is that a excessive voltage stress due to the link voltage increase can be suppressed by removing link capacitor and suggest new 'Level-shifting switch driver'. this new gate driver is improved 66% of efficiency than switching loss of a existed push-pull amplifier. The proposed converter is tested with a 400W(200V-2A output) prototype circuit.

• Journal of the Semiconductor & Display Technology
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• v.5 no.3 s.16
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• pp.11-16
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• 2006

A low cost PDP sustain power supply is proposed based on flyback topology. By using Boundary Conduction Method(BCM) to control input current regulation, DCM condition can be met under all load conditions. Another feature of the proposed method is that a excessive voltage stress due to the link voltage increase can be suppressed by removing link capacitor and suggest new 'Level-shifting switch driver'. this new gate driver is improved 66% of efficiency than switching loss of a existed push-pull amplifier. The proposed converter is tested with a 400W(200V-2A output) prototype circuit.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.561-562
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• 2006

This paper presents an SRAM which uses the technique to equalize the internal cell node by adding an NMOS transistor. Accordingly, the write driver operates rapidly in a differential current of bit lines, and the operation speed of SRAM improves. An SRAM was implemented with a memory cell, a sense amplifier and a write driver. The SRAM obtained the performance of 18% power reduction and improvement of 56% operation speed. And Power delay product was reduced with 63%. The proposed SRAM was designed based on a 0.35um 1P4M CMOS technology.

• Journal of Industrial Technology
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• v.32 no.A
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• pp.109-114
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• 2012

In this paper, We studied LED(Light Emitted Diode) sensor lights system using PIR(Pyroelectric Infrared Ray) sensor, CdS and MCU(Micro Controller Unit). And applied the valley fill circuit to improve the power factor. We designed the amplifier for each sensor and the LED driver for constant current which is the buck converter. Also, we proposed the algorithm of LED control by each sensors using MCU. Experimental results showed that power factor is 92% with valley fill circuit.