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http://dx.doi.org/10.6109/jkiice.2019.23.6.719

A 2.4-GHz Dual-Mode CMOS Power Amplifier with a Bypass Structure Using Three-Port Transformer to Improve Efficiency  

Jang, Joseph (School of Electronic Engineering, Soongsil University)
Yoo, Jinho (School of Electronic Engineering, Soongsil University)
Lee, Milim (School of Electronic Engineering, Soongsil University)
Park, Changkun (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.23, no.6, 2019 , pp. 719-725 More about this Journal
Abstract
We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.
Keywords
Cascode; driver stage; dual mode; power amplifier; transformer;
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