• Title/Summary/Keyword: Drain-source contacts

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The Manufacture of Conductive paste for OTFT source & drain contacts Fabricated by Direct printing method (Direct Printing법에 의해 제작된 OTFT용 source & drain 전극용 전도성 페이스트 제조)

  • Lee, Mi-Young;Nam, Su-Yong;Kim, Seong-Hyun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.384-385
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    • 2006
  • We studied about conductive pastes of the source-drain contacts for OTFTs(organic thin-film transistors) fabricated by direct printing(screen printing) method. We used Ag and conductive carbon black powder as the conductive fillers of pastes. The conductive pastes were manufactured by various dispersing agents and dispersing conditions and source-drain contacts with $100{\mu}m$ of channel length were fabricated. We could obtain the OTFTs which exhibited different field-effect behaviors over a range of source-dram and gate voltages depending on a kind of conductive fillers used conductive pastes.

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A Study on Contacts for Organic thin-film transistors fabricated by Screen Printing Method (스크린 인쇄법에 의해 제작된 유기 박막 트랜지스터용 전극에 관한 연구)

  • Lee Mi-Young;Nam Su-Yong
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2006.05a
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    • pp.591-592
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    • 2006
  • We studied about the manufacture of the drain-source contacts for OTFTs(organic thin-film transistors) by using screen printing method. The conductive fillers used Ag and carbon black. The conductive contacts with $100{\mu}m$ of channel length were screen printed on a silicon dioxide gate dielectric layer and, the pentacene semiconductor was deposited via vacuum deposition. As a result of studying various conductive pastes, we could obtain the OTFTs which exhibited field-effect behavior over arrange of drain-source and gate voltages, similar to devices employing deposited Au contacts. By using screen-printing with conductive paste, the contacts are processed at low temperature, thereby facilitating their integration with heat sensitive substrates.

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Electrical Characteristics and Models for Asymmetric n-MOSFET′s with Irregular Source/Drain Contacts (불규칙한 소오스/드레인 금속 접촉을 갖는 비대칭 n-MOSFET의 전기적 특성 및 모델)

  • 공동욱;정환희;이재성;이용현
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.208-211
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    • 1999
  • Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

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Design and Fabrication of Flexible OTFTs by using Nanocantact Printing Process (미세접촉프린팅 공정을 이용한 유연성 유기박막소자(OTFT)설계 및 제작)

  • Jo Jeong-Dai;Kim Kwang-Young;Lee Eung-Sug;Choi Byung-Oh;Esashi Masayoshi
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.506-508
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    • 2005
  • In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

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Screen-printed Source and Drain Electrodes for Inkjet-processed Zinc-tin-oxide Thin-film Transistor

  • Kwack, Young-Jin;Choi, Woon-Seop
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.6
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    • pp.271-274
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    • 2011
  • Screen-printed source and drain electrodes were used for a spin-coated and inkjet-processed zinc-tin oxide (ZTO) TFTs for the first time. Source and drain were silver nanoparticles. Channel length was patterned using screen printing technology. Different silver nanoinks and process parameters were tested to find optimal source and drain contacts Relatively good electrical properties of a screen-printed inkjet-processed oxide TFT were obtained as follows; a mobility of 1.20 $cm^2$/Vs, an on-off current ratio of $10^6$, a Vth of 5.4 V and a subthreshold swing of 1.5 V/dec.

Effects of Pentacene Thickness and Source/Drain Contact Location on Performance of Penatacene TFT (펜타센 박막의 두께와 전극위치가 펜타센 TFT 성능에 미치는 영향)

  • 이명원;김광현;송정근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1001-1007
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    • 2002
  • In this paper we analyzed the effects of pentacene thickness and the location of source/drain contacts on the performance of pentacene TFT Above a certain thickness of pentacene thin film the pentacene grain was turned from the thin film phase into the bulk phase, resulting in degrading the crystallinity and then performance as well. For the top contact structure in which source/drain contacts are located above pentacene film, the contact resistance decreased comparing with the bottom contact structure. However, the leakage current in the off-state became large and then the related parameters such as on/off current ratio were deteriorated. We found that the thickness of around 300$\AA$-700$\AA$ was suitable, and that the bottom contact was more feasible for hig Performance pentacene OTFT.

Performance Improvement of Amorphous In-Ga-Zn-O Thin-film Transistors Using Different Source/drain Electrode Materials (서로 다른 소스/드레인 전극물질을 이용한 비정질 In-Ga-Zn-O 박막트랜지스터 성능향상)

  • Kim, Seung-Tae;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.2
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    • pp.69-74
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    • 2016
  • In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

Analysis for Series Resistance of Amorphous Silicon Thin Film Transistor (비정질 실리코 박막 트랜지스터의 직렬 저항에 관한 분석)

  • Kim, Youn-Sang;Lee, Seong-Kyu;Han, Min-Koo
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.6
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    • pp.951-957
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    • 1994
  • We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

Analysis on the breakdown characteristics of ESD-protection NMOS transistors based on device simulations (소자 시뮬레이션을 이용한 ESD 보호용 NMOS 트랜지스터의 항복특성 분석)

  • 최진영;임주섭
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.11
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    • pp.37-47
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    • 1997
  • Utilizing 2-dimensional device simulations incorporating lattic eheating models, we analyzed in detail the DC breakdown characterisics of NMOS trasistors with different structures, which are commonly used as ESD protection transistors. The mechanism leading to device failure resulting from electrostatic discharge was explained by analyzing the 1st and 2nd breakdown characteristics of LDD devices. Also a criteria for more robust designs of NMOS transistor structures against ESD was suggested by examining the characteristics changes with changes in structural parameters such as the LDD doping concentration, the drain junction depth, the distance between source/drain contacts, and the source junction area.

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