• 제목/요약/키워드: Drain engineering

검색결과 987건 처리시간 0.033초

해수침투 지역의 염분농도 분포 파악 및 전기비저항의 상관성분석 사례 (Rapid estimation of salinity in seawater intrusion zones and correlation analysis between resistivity and salinity)

  • 정래철;김정호;김기석;김종훈;안희윤
    • 한국지구물리탐사학회:학술대회논문집
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    • 한국지구물리탐사학회 2007년도 공동학술대회 논문집
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    • pp.307-312
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    • 2007
  • Seawater intrusion in estuarine regions is an important issue in protecting groundwater against salinity increase as well as in protecting construction materials against corrosion. For example, drain water ejected during accelerated consolidation for the improvement of soft ground can cause damages to farm land because the drain water from seawater intrusion zones contains salinity. In this study, we have employed correlation analysis between resistivity value and salinity of in situ pore water. The correlation analysis indicates that resistivity and salinity are in exponential relationship with good correlation. Therefore we suggest that rapid estimation of spatial distribution of NaCl is possible using resistivity data.

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Impact of LDD Structure on Single-Poly EEPROM Characteristics

  • Na, Kee-Yeol;Park, Mun-Woo;Kim, Kyung-Hoon;Kim, Nan-Soo;Kim, Yeong-Seuk
    • Journal of Electrical Engineering and information Science
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    • 제3권3호
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    • pp.391-395
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    • 1998
  • The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8$\mu\textrm{m}$ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.

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자동 저수와 배수가 가능한 중량 우량계 용 쌍수조 (A Paired Barrel Capable of Automatic Storage and Emptying of Water for a Weighing Raingauge)

  • 임규호;임은옥
    • 대기
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    • 제27권2호
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    • pp.251-258
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    • 2017
  • The standard weighing raingauges have a capacity limit in measuring the amounts of precipitation. Exceptions are those using a siphon to drain the collected water during observations. To reduce the drain time of the siphon type or to overcome the hassles associated with the manual emptying of the bucket for measuring, the most of weighing gauges use a large bucket for storing of rainwater to be measured. To avoid the above-mentioned adverse requirements, we propose a paired barrel for a weighing raingauge. The paired barrel may improve the accuracy of the weighing raingauges by getting rid of their capacity limit and make the gauges smaller in size and lighter in weight than the conventional ones. We showed its proper function and the feasibility of realization by testing a prototype paired barrel.

Experinces with Soft Clay Improvement in the Bangkok plain

  • O, P-R
    • 한국지반공학회:학술대회논문집
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    • 한국지반공학회 1997년도 Lecture Notes by Two Distinguished Scholars
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    • pp.1.1-16
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    • 1997
  • This lecture summarizes the progress of the development of the different ground improvement techniques in Bangkok Plain and is reviewed in relation to the extensive deep wen pumping and the resulting piezometric drawdown at deeper depths. Case records of test embankments with sand drains, sand wicks and PVD are presented to inustrate the effectiveness of different types of vertical drains with surcharge. The use of prefsbicated drain seems more superior than the other types of sand drain. Construction of test embaxlkment, criteria for PVD selection and relevant laboratory testing techniques are discussed for formulating the specif'ication. Alternative teckuuque, such in, the use of deep chemical mixing is reviewed in terms of the efficiency of cement, lime and flyash as additive. Vacuum pre-loading with surcharge and elctro- osmotic consolidation are also explored as possible tectmiques to improve the engineering properties of soft Bangkok clay.

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전극에 따른 유기박막트랜지스터 소자의 전기적 특성 연구 (Study on Organic Thin-Film Transistors(OTFTs) Devices with Gold and Nickel/Silver electrodes)

  • 황선욱;형건우;박일홍;최학범;김영관
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.271-272
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    • 2008
  • We fabricated a pentacene thin-film transistor with Ni/Ag source/drain electrodes. Also, we obtained similar electrical characteristics as compared with source/drain electrode with Au. This device was found to have a field-effect mobility of about 0.021 $cm^2$/Vs, a threshold voltage of -5, -7 V, an subthreshold slope of 2.0, 4.5 V/decade, and an on!off current ratio of $3.6\times10^5$, $2.0\times10^6$.

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Hysteresis Characteristics in Low Temperature Poly-Si Thin Film Transistors

  • Chung, Hoon-Ju;Kim, Dae-Hwan;Kim, Byeong-Koo
    • Journal of Information Display
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    • 제6권4호
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    • pp.6-10
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    • 2005
  • The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.

다결정 실리콘 박막 트랜지스터의 수소화에 따른 전기적 스트레스의 영향 (Effects of Electrical Stress on Polysilicon TFTs with Hydrogen Passivation)

  • 황성수;황한욱;김용상
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제48권5호
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    • pp.367-372
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    • 1999
  • We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

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Enhanced Electrical Performance of SiZnSnO Thin Film Transistor with Thin Metal Layer

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • 제18권3호
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    • pp.141-143
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    • 2017
  • Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

XPS Study of MoO3 Interlayer Between Aluminum Electrode and Inkjet-Printed Zinc Tin Oxide for Thin-Film Transistor

  • Choi, Woon-Seop
    • Transactions on Electrical and Electronic Materials
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    • 제12권6호
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    • pp.267-270
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    • 2011
  • In the process of inkjet-printed zinc tin oxide thin-film transistor, the effect of metallic interlayer underneath of source and drain electrode was investigated. The reason for the improved electrical properties with thin molybdenum oxide ($MoO_3$) layer was due to the chemically intermixed state of metallic interlayer, aluminum source and drain, and oxide semiconductor together. The atomic configuration of three Mo $3d_3$ and $3d_5$ doublets, three different Al 2p core levels, two Sn $3d_5$, and four different types of oxygen O 1s in the interfaces among those layers was confirmed by X-ray photospectroscopy.

공차해석을 이용한 에어컨 실내기의 조립성에 관한 연구 (Study of the Assembly of Indoor Air-conditioner Unit Using Tolerance Analysis)

  • 김철곤;황지훈;서형준;모진용;정두한;홍석무
    • 대한기계학회논문집A
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    • 제39권4호
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    • pp.423-428
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    • 2015
  • 에어컨 실내기 조립 시 부품간 간섭이 발생하는 위치와 원인 분석을 위해, 3차원 공차해석을 수행하고 부품공차 및 조립 갭을 최적화했다. 민감도 분석을 통해 초기 설계에서 drain과 body 조립부의 불량발생 확률이 72.6%로 가장 높은 것을 확인했고, 또한 유한요소해석(FEA)을 활용 에어컨 실내기의 난방작동 시 열 변형으로 인해 최대 약 1mm의 변위가 발생하여 부품간 간섭이 발생할 수 있음을 확인했다. 이런 부품간 간섭을 최소화기 위해서 3D 공차 해석의 민감도 분석결과를 토대로 drain의 부품공차를 수정하였다. 개선 공차 반영 해석결과 불량률이 0.03%로 크게 감소함을 확인하였다. 또한, 개선공차 반영 시 에어컨 작동 중 열 변형이 발생하여도 부품간 간섭이 발생하지 않음을 FEA를 통해 검증하였다.