• Title/Summary/Keyword: Drain engineering

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Engineering Characteristics of Horizontal Drainage for Stabilization of Dredged Fill (준설매립지반의 안정처리를 위한 수평배수재의 공학적 특성)

  • 이상호;박정용;장연수;박정순;김수삼
    • Proceedings of the Korean Geotechical Society Conference
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    • 2001.03a
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    • pp.563-570
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    • 2001
  • In this study, the charactersistics of horizontal drains used to stabilize the dredged fill are investigated experimentally by doing tensile strength test, discharge capacity test, and filter clogging test. The types of the drains selected for the study are filament type (Tyre-E), embossed type(Type-P) and heat bonded cubic type with the thickness 10mm(Type-010) and 5mm(Type-05). The results of tensile strength and discharge capacity test show that the performance of drain Type-O10 was better than the other drains. This is caused by the fact that the lattice shape core of drain Type-O10 has strong rigidity and minimizes the loss of the sectional area of discharge with increased confining pressure. Analyzing the compatibility of filters by the results of the strength characteristics test and clogging test, the filter of filament type drain produced with polyester clothed polyamide performed well.

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Fabrication and Characterization of Self-Aligned Recessed Channel SOI NMOSFEGs

  • Lee, Jong-Ho
    • Journal of Electrical Engineering and information Science
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    • v.2 no.4
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    • pp.106-110
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    • 1997
  • A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

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Effect of Loading Rate to Bearing Capacities (지지력에 미치는 재하속도에 관한 해석적 연구)

  • 박중배
    • Geotechnical Engineering
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    • v.13 no.1
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    • pp.147-158
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    • 1997
  • In this study, it is examined that partial drain has an effect of bearing capacities and deformations on intermediate soils. To compare the numerical and experimental results, this study uses CRISP90 which is composed of Modify Cam-Clay Model for calculation and Geotechnical Centrifuge in model test. As the results of analysis, we can classify relative loading rate into three ranges which are drain, undrain and partial drain. Besides it is proved that partial drain range is about 103.

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Modeling of Parasitic Source/Drain Resistance in FinFET Considering 3D Current Flow (3차원적 전류 흐름을 고려한 FinFET의 기생 Source/Drain 저항 모델링)

  • An, TaeYoon;Kwon, Kee-Won;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.10
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    • pp.67-75
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    • 2013
  • In this paper, an analytical model is presented for the source/drain parasitic resistance of FinFET. The parasitic resistance is a important part of a total resistance in FinFET because of current flow through the narrow fin. The model incorporates the contribution of contact and spreading resistances considering three-dimensional current flow. The contact resistance is modeled taking into account the current flow and parallel connection of dividing parts. The spreading resistance is modeled by difference between wide and narrow and using integral. We show excellent agreement between our model and simulation which is conducted by Raphael, 3D numerical field solver. It is possible to improve the accuracy of compact model such as BSIM-CMG using the proposed model.

A Study on the Temperature Characteristics at the Inlet and the Outlet Pipes of a Refrigerator Drain Condenser (냉장고 배출수 응축기 입출구 배관에서의 온도 특성에 관한 연구)

  • Ha, Ji Soo;Kim, Tae Kwon
    • Journal of Energy Engineering
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    • v.23 no.4
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    • pp.247-255
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    • 2014
  • The present study was conducted to elucidate the characteristics of temperature at the inlet and outlet pipes of a refrigerator drain condenser and suggest the method to predict the temperature of the refrigerant at the inlet and outlet pipes of the drain condenser. For this purpose, a built in style refrigerator was installed in a constant temperature chamber to measure temperatures at the inlet and outlet pipes of the drain condenser. From the results of the present analysis, it could be seen that the measured temperatures changed from $37^{\circ}C$ to $46^{\circ}C$ and the actual refrigerant temperatures were higher than the measured temperatures with the difference magnitude of $8^{\circ}C$ to $22^{\circ}C$. The present study suggested that the temperatures of the refrigerator could be calculated with the measured temperatures by introducing curve fitting of the measured temperature. The predicted refrigerant temperatures by the present study had the accuracy within 6% error of the actual refrigerant temperatures.

Design of a Gate-VDD Drain-Extended PMOS ESD Power Clamp for Smart Power ICs (Smart Power IC를 위한 Gate-VDD Drain-Extened PMOS ESD 보호회로 설계)

  • Park, Jae-Young;Kim, Dong-Jun;Park, Sang-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.1-6
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    • 2008
  • The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

Numerical Analysis on Drain Capacity and Vegetation Potential of Unsaturated Made-Planting Soil (불포화 인공 식재 지반의 배수 성능과 식생 가능 조건에 대한 수치해석적 분석)

  • Kim, Sung-Min;Kim, Choong-Eon;Jung, Young-Hoon
    • Journal of the Korean GEO-environmental Society
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    • v.17 no.6
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    • pp.33-41
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    • 2016
  • This study attempted to investigate drain capacity and vegetation potential of made-planting soil via finite element simulations. Engineering drain capacity of made-planting soil can be evaluated by an analysis of unsaturated soils. In a perspective for vegetation landscape, it is necessary to check whether the minimum amount of water in the made-planting soil can be supplied for the survival of plants. Herein, 1-m high soil column covered by made-planting soil were numerically simulated. Numerical results showed that how the coefficient of permeability of saturated soil and soil-water characteristics of unsaturated soil are considered significantly influences the drain capacity of soils. Variation in the volumetric water content within the Least Limiting Water Range (LLWR) provides us with information on whether the soil can contain a sufficient amount of water for the plants to survive the drought.

Performance Analysis of Tri-gate FinFET for Different Fin Shape and Source/Drain Structures (Tri-gate FinFET의 fin 및 소스/드레인 구조 변화에 따른 소자 성능 분석)

  • Choe, SeongSik;Kwon, Kee-Won;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.7
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    • pp.71-81
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    • 2014
  • In this paper, the performance variations of tri-gate FinFET are analyzed for different fin shapes and source/drain epitaxy types using a 3D device simulator(Sentaurus). If the fin shape changes from a rectangular shape to a triangular shape, the threshold voltage increases due to a non-uniform potential distribution, the off-current decreases by 72.23%, and the gate capacitance decreases by 16.01%. In order to analyze the device performance change from the structural change of the source/drain epitaxy, we compared the grown on the fin (grown-on-fin) structure and grown after the fin etch (etched-fin) structure. 3-stage ring oscillator was simulated using Sentaurus mixed-mode, and the energy-delay products are derived for the different fin and source/drain shapes. The FinFET device with triangular-shaped fin with etched-fin source/drain type shows the minimum the ring oscillator delay and energy-delay product.

Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 도핑분포함수에 따른 DIBL)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2643-2648
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    • 2015
  • This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

Development of a 2.14-GHz High Efficiency Class-F Power Amplifier (2.14-GHz 대역 고효율 Class-F 전력 증폭기 개발)

  • Kim, Jung-Joon;Moon, Jung-Hwan;Kim, Jang-Heon;Kim, Il-Du;Jun, Myoung-Su;Kim, Bum-Man
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.873-879
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    • 2007
  • We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the $2^{nd}\;and\;3^{rd}$ harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.