• Title/Summary/Keyword: Drain engineering

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Design of L-Band High Speed Pulsed High Power Amplifier Using LDMOS FET (LDMOS FET를 이용한 L-대역 고속 펄스 고전력 증폭기 설계)

  • Yi, Hui-Min;Hong, Sung-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.4
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    • pp.484-491
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    • 2008
  • In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.

The Design of Low Noise Downconverter for K-band Satellite Multipoint Distribution Service (K-band SMDS용 저잡음 하향변환기의 설계)

  • 정인기;이영철;김천석
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.5 no.6
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    • pp.1143-1150
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    • 2001
  • In this paper, we designed a downconverter for K-band satellite multipoint distribution service(SMDS). The designed downconverter consists of a low noise amplifiers, bandpass filter, stable local oscillator, drain mixer and If Amplifiers. Low noise amplifiers show 28㏈ gain and 1.5㏈ noise figure in the frequency range of 19.2㎓~20.2㎓, and a band pass filter has a -l㏈ insertion loss, and 18.25㎓ Stable local oscillator which is dielectric resonant oscillation, We obtained that the output power of the 18.25㎓ oscillation frequency is 0.5㏈m and the phase noise is the -84.67㏈c at 10KHz offset frequency. With the input RF signal the 19.2㎓~20.2㎓, conversion gain of the drain mixer shows 5㏈ at the Intermediate frequency range of 950MHz~1950MHz. We have proved that the designed downconverter satisfied the specification of a K-band satellite multipoint distribution service and it can be applied to the satellite internet receiver.

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Variation of the structural stability for the sonar dome window in a naval vessel according to the state of the drain valve (소나돔 충, 배수 밸브의 상태에 따른 함정용 소나돔 윈도우의 구조안정도 변화)

  • Han, HyungSuk;Lee, KyungHyun;Park, SeongHo;Lim, YongSoo
    • Journal of Advanced Marine Engineering and Technology
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    • v.38 no.7
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    • pp.844-853
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    • 2014
  • Since the active sonar for a naval vessel is usually installed in a bulbous bow, GRP(Glass reinforced plastic) material with low density and high strength is used for the material of the sonar dome window in order to prohibit impact by slamming wave or foreign material in the sea. The structural safety of the sonar dome is varied according to the interior and exterior distributed pressure on the sonar dome. Therefore, the variation of the structural safety according to the pressure variation of the sonar dome window caused by the drain valve state is studied by CAE.

Relation of Oxide Thickness and DIBL for Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET에서 산화막 두께와 DIBL의 관계)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.4
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    • pp.799-804
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    • 2016
  • To analyze the phenomenon of drain induced barrier lowering(DIBL) for top and bottom gate oxide thickness of asymmetric double gate MOSFET, the deviation of threshold voltage is investigated for drain voltage to have an effect on barrier height. The asymmetric double gate MOSFET has the characteristic to be able to fabricate differently top and bottom gate oxide thickness. DIBL is, therefore, analyzed for the change of top and bottom gate oxide thickness in this study, using the analytical potential distribution derived from Poisson equation. As a results, DIBL is greatly influenced by top and bottom gate oxide thickness. DIBL is linearly decreased in case top and bottom gate oxide thickness become smaller. The relation of channel length and DIBL is nonlinear. Top gate oxide thickness more influenced on DIBL than bottom gate oxide thickness in the case of high doping concentration in channel.

A Study on Rain Gutters with Coanda Effect (코안다효과가 적용된 빗물받이에 관한 연구)

  • Jung, Yong Sin;Kim, Yong Sun;Shin, Hee Jae;Ko, Sang Cheol
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.19 no.4
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    • pp.58-64
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    • 2020
  • Large-scale flooding due to extreme weather and typhoons causes heavy damage. This is especially true in urban areas where accumulated debris prevents the smooth drainage of rainwater in sewage facilities such as rain gutters installed near roads. In this study, to improve the drainage performance and effectively remove foreign substances by applying the dust screen used in rivers, the rain gutter with Coanda effect was simulated and compared with the experiment. The simulation was performed by setting the parameters to the fillet radius R1 and R2 at the top of the screen filter, the fillet radius R3 at the bottom of the screen filter, and the height H of the gap W from the bottom. W is the gap at the backside of screen filter which is applied to stimulate the Coanda effect. According to the simulation results, the highest drain performance was 87.99% derived from R1= 30mm, R2= 5mm, R3= 85mm, H= 75mm, and W= 2mm. The error rate of simulation results refer to the 4.89%~7.36% compared to the experimental results. In the future, by considering the slope according to the installation environment, the simulation results can be applied to the actual roadside to help prevent flood damage.

A Fast-Switching Current-Pulse Driver for LED Backlight (LED 백라이트를 위한 고속 스위칭 전류-펄스 드라이버)

  • Yang, Byung-Do;Lee, Yong-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.39-46
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    • 2009
  • A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

Optimization of Design Parameters for Steel Grating Using Taguchi Method Considering Rigidity and Drainage Efficiency (다구찌기법 기반의 강성과 배수능력 관계를 고려한 스틸그레이팅의 설계변수 최적화)

  • Kim, Woo-Tae;Lee, Se-Jin
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.38 no.8
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    • pp.905-910
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    • 2014
  • The steel grating discussed in this study is a drain cover that enhances the rigidity of the steel frame using an inclined inflow tract for wastewater, facilitates smooth drainage, and prevents the escape of bad smell from the drain. Recently, the urban problem of bad smell in sewerage lines has been hindering the improvement of living standards. Moreover, the frequent failure of existing products deters bad smell prevention measures and results in administrative power and budget wastage. The pressure to reduce budgets propels the increased demand for functional steel grating. Thus, this study focused on optimizing the design parameters of a steel grating by simultaneously considering its rigidity and drainage efficiency.

Relation of Short Channel Effect and Scaling Theory for Double Gate MOSFET in Subthreshold Region (문턱전압이하 영역에서 이중게이트 MOSFET의 스켈링 이론과 단채널효과의 관계)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.7
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    • pp.1463-1469
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    • 2012
  • This paper has presented the influence of scaling theory on short channel effects of double gate(DG) MOSFET in subthreshold region. In the case of conventional MOSFET, to preserve constantly output characteristics,current and switching frequency have been analyzed based on scaling theory. To analyze the results of application of scaling theory for short channel effects of DGMOSFET, the changes of threshold voltage, drain induced barrier height and subthreshold swing have been observed according to scaling factor. The analytical potential distribution of Poisson equation already verified has been used. As a result, it has been observed that threshold voltage among short channel effects is grealty changed according to scaling factor. The best scaling theory for DGMOSFET has been explained as using modified scaling theory, applying weighting factor reflected the influence of two gates when scaling theory has been applied for channel length.

Consolidation Analysis for PVD Installed Soft Ground Using a Modified Theoretical Solution (변형된 이론해를 이용한 연직배수재 설치 지반의 압밀해석)

  • Hong, Sung-Jin;Kim, Dong-Hee;Kim, Yun-Tae;Kim, Hyung-Sub;Lee, Woo-Jin
    • Journal of the Korean Geotechnical Society
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    • v.28 no.1
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    • pp.41-53
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    • 2012
  • As the permeability of soil adjacent to the vertical drain has a decisive effect on the rate of consolidation, the permeability of smear zone governs the rate of radial consolidation of PVD installed soft ground. In this study, a method was suggested to analyze the radial consolidation, based on consolidation characteristics of remolded clay, and was used to evaluate the consolidation of soft clay layer in Busan Newport. The suggested method provides more reliable consolidation behaviors than the conventional approach, which is based on the consolidation characteristics of undisturbed clay. The suggested method is also observed to be relatively insensitive to the uncertainty of $k_h/k_s$. The comparison between the analysis and field measurement revealed that the suggested method provided a reliable prediction on the rate of consolidation of PVD installed Busan new port clay and that an appropriate extent of smear zone was evaluated as about $3d_w$ by back analysis.

Analysis of Subthreshold Characteristics for Double Gate MOSFET using Impact Factor based on Scaling Theory (스켈링이론에 가중치를 적용한 DGMOSFET의 문턱전압이하 특성 분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.2015-2020
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    • 2012
  • The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.