• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.325-330
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• 2012

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel structure and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model. Resultly, DIBL has been greatly changed for channel structure and doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1123-1127
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• 2009

This paper expands the scope of application of the thin film transistor (TFT) in which it is used as the switching element by making the amorphous silicon TFT with the non-volatile memory device,. It is the thing about the amorphous silicon non-volatile memory device which is suitable to an enlargement and in which this uses the additionally cheap substrate according to the amorphous silicon use. As to, the amorphous silicon TFT non-volatile memory device is comprised of the glass substrates and the gate, which evaporates on the glass substrates and in which it patterns the first insulation layer, in which it charges the gate the floating gate which evaporates on the first insulation layer and in which it patterns and the second insulation layer in which it charges the floating gate, and the active layer, in which it evaporates the amorphous silicon on the second insulation layer the source / drain layer which evaporates the n+ amorphous silicon on the active layer and in which it patterns and the source / drain layer electrode in which it evaporates on the source / drain layer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1717-1723
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• 2007

In this study , quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) devices are fabricated using PLZT(10/30/70), PLT(10), PZT(30/70) thin film and their drain current properties are investigated. It is found that the drain current of quasi-MFISFET is directly influenced by the polarization strength of ferroelectric thin fan. Also, when the gate voltages are ${\pm}5\;and\;{\pm}10V$, the memory windows are 0.5 and 1.3V, respectively. It means that the memory window is changed with the variation of coercive voltage generated by the voltage applied on ferroelectric thin film. The electric field and the leakage current with time delay of PLZT(10/30/70) thin lam are measured to investigate the retention property of MFISFET device. Some material parameters such as current density constant, $J_{ETO}$, electric field dependent factor K and time dependent factor m are obtained. The variation of charge density with time is quantitatively analyzed by using the material parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.358-364
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• 2009

This paper shows some variable bias techniques which can improve the power added efficiency(PAE) for the designed power amplifier. Some simulations have been done to get the effect of the bias change, and variable bias is adopted to get the higher efficiency for dual mode amplifier which generates two different output power levels. With drain bias change and a fixed gate bias, the amplifier shows PAE improvement compared to the fixed bias amplifier. In addition, this paper analyzed nonlinear distortion of the power amplifier and has used the digital predistortion which can result in 10dB ACPR improvement for the dual band amplifier.

• Journal of Information Display
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• v.10 no.3
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• pp.131-136
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• 2009

This is a report on the fabrication of a flexible OTFT backplane for electrophoretic display (EPD) using a printing technology. A practical printing technology for a polycarbonate substrate was developed by combining the conventional screen and inkjet printing technologies with the wet etching and oxygen plasma processes. For the gate electrode, the screen printing technology with Ag ink was developed to define the minimum line width of ${\sim}5{\mu}m$ and the thickness of ${\sim}70nm$ with the resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, which are suitable for displays with SVGA resolution. For the source and drain (S/D) electrodes, PEDOT:PSS, whose conductivity was drastically enhanced to 450 S/cm by adding 10 wt% glycerol, was adopted. In addition, the modified PEDOT:PSS could be neatly confined in the specific S/D electrode area that had been pretreated with oxygen. The OTFTs that made use of the developed printing technology produced a mobility of ${\sim}0.13cm^2/Vs.ec$ and an on/off current ratio of ${\sim}10^6$, which are comparable to those using thermally evaporated Au for the S/D electrode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.617-621
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• 2013

This study examined the effect of electron-beam (E-beam) irradiation on the electrical properties of n-GaN, AlGaN and AlGN/GaN structures on sapphire substrates. E-beam irradiation resulted in a significant decrease in the gate leakage current of the n-GaN, AlGaN and HEMT structure from $4.0{\times}10^{-4}A$, $6.5{\times}10^{-5}A$, $2.7{\times}10^{-8}A$ to $7.7{\times}10^{-5}A$, $7.7{\times}10^{-6}A$, $4.7{\times}10^{-9}A$, respectively, at a drain voltage of -10V. Furthermore, we also investigated the effect of E-beam irradiation on the AlGaN surface in AlGaN/GaN heterostructure high electron mobility transistors(HEMTs). The results showed that the maximum drain current density of the AlGaN/GaN HEMTs with E-beam irradiation was greatly improved, when compared to that of the AlGaN/GaN HEMTs without E-beam irradiation. These results strongly suggest that E-beam irradiation is a promising method to reduce leakage current of AlGaN/GaN HEMTs on sapphire through the neutralization the trap.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.1-7
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• 2010

The device performances of accumulation-mode Pi-gate pMOSFETs with different fin widths have been characterized at high operating temperatures. The device fin height is 10nm and fin widths are 30nm, 40nm, and 50nm. The variation of the drain current, threshold voltage, subthreshold swing, effective mobility, and leakage current have been investigated as a function of operating temperatures. The drain current at high temperature is slightly larger than at room temperature. The variation of the threshold voltage as a function of the operating temperature is smaller than that of the inversion-mode MOSFETs. The effective mobility is decreased with the increase of operating temperature. It is observed that the effective mobility is enhanced as the fin width decreases.