• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.403-404
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• 2012

We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.280-281
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• 2011

We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.9
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• pp.21-30
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• 1999

Halo pocket implantation in MOSFETs, which is known to be an efficient method to provent the punchthrough and threshold voltage roll-off phenomena, decreases the drain current of MOSFET devices. Although the decrease of the drain current in halo structure MOSFET is usually explained in terms of the increase of the threshold voltage, more decrease in the drain current than is predicted by the increased threshold voltage has experimentally been observed. In this work, the effect of halo doping profile on the drain current degradation is investigated in terms of the field distribution along the channel. Effective mobility model of the halo MOSFETs due to pocket implantation is presented and the degradation of the mobility is shown to be effective in the further decrease of the drain current. Present model is shown to be in good agreement with experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.2
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• pp.69-74
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• 2016

In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.959-964
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• 2018

In this paper, it was firstly confirmed that the drain current of the depleted SOI MOSFET operated in the high frequency response delay occurs by the inductive parasitic. Depleted SOI MOSFET cannot be applied as a conventional high-frequency MOSFET model because the response delay of the drain current is generated in accordance with the drain voltage fluctuation. This response delay may be described as a non-quasi-static effect, and the SOI MOSFET generated the response delay by the inductive parasitics compared to typical MOSFET. It is confirmed that depleted SOI MOSFET's RF characteristics can be well reproduced with the proposed method including the drain current response delay.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.487-489
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• 2017

Source와 Drain 부분에 도핑의 농도를 변화시킴으로써 MOSFET의 내부의 Total current의 변화의 경향성을 분석하였다. 이를 위해 Simple한 MOSFET 구조를 설계를 한 뒤 gate 부분에 전압을 주어 측정을 하였으며, 그 결과 Source, Drain의 도핑농도가 증가 될 수록 Total current의 변화하는 정도가 커짐을 알 수 있다.