• 한국압력기기공학회 논문집
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• 제6권2호
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• pp.20-27
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• 2010

In order to prevent the corrosion of component contacted primary water designed alloy 600 material in the nuclear power plant. But the primary water stress corrosion cracking(PWSCC) of alloy 600 and weld area occurs continuously due to the residual stress. The leakage accident resulted from PWSCC in the drain nozzle of the steam generator of domestic power plants. Heater sleeves of the pressurizer are welded with alloy 600 weld material and therefore exposed to the primary water environment. PWSCC occurred in heater sleeve material and weld area of many foreign power plants. The current issue of domestic nuclear power plants are consequently concentrated to PWSCC of similar material. In order to improve the detection and the sizing of the PWSCC in the welding sleeve of the pressurizer, the automatic UT system and multi-directions probe sets have been developed. The experimental studies have been performed using the mock-up block containing artificial reflectors(ID connected EDM notch) and semi-artificial cracks made from thermal fatigue. The automatic UT System is applied in the detection and the length sizing of the ID/OD on the tube and the J-groove weld area of the artificial reflectors and results of the detection and the sizing are compared respectively. Also, the developed automatic UT system is successfully accomplished to inspect the heater sleeve and the J-groove weld area on the pressurizer for the detection of PWSCC.

• ETRI Journal
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• 제37권6호
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• pp.1135-1142
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• 2015

Multilayered ZnO-$SnO_2$ heterostructure thin films consisting of ZnO and $SnO_2$ layers are produced by alternating the pulsed laser ablation of ZnO and $SnO_2$ targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and $SnO_2$ layers. The performance parameters of amorphous multilayered ZnO-$SnO_2$ heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and $SnO_2$ layers. A highest electron mobility of $43cm^2/V{\cdot}s$, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of $10^{10}$ are obtained for the amorphous multilayered ZnO(1.5nm)-$SnO_2$(1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO-$SnO_2$ heterostructure film consisting of ZnO, $SnO_2$, and ZnO-$SnO_2$ interface layers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.227-228
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• 2006

In this paper, we introduce the design and fabrication of 60 GHz low noise amplifier MMIC for IEEE802.15.3c WPAN system. The 60 GHz LNA was designed using ETRI's $0.12{\mu}m$ PHEMT process. The PHEMT shows a peak transconductance ($G_{m,peak}$) of 500 mS/mm, a threshold voltage of -1.2 V, and a drain saturation current of 49 mA for 2 fingers and $100{\mu}m$ total gate width (2f100) at $V_{ds}$=2 V. The RF characteristics of the PHEMT show a cutoff frequency, $f_T$, of 97 GHz, and a maximum oscillation frequency, $f_{max}$, of 166 GHz. The performances of the fabricated 60 GHz LNA MMIC are operating frequency of $60.5{\sim}62.0\;GHz$, small signal gain ($S_{21}$) of $17.4{\sim}18.1\;dB$, gain flatness of 0.7 dB, an input reflection coefficient ($S_{11}$) of $-14{\sim}-3\;dB$, output reflection coefficient ($S_{22}$) of $-11{\sim}-5\;dB$ and noise figure (NF) of 4.5 dB at 60.75 GHz. The chip size of the amplifier MMIC was $3.8{\times}1.4\;mm^2$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.623-624
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• 2006

In this paper, we introduce the design and fabrication of V-band power amplifier MMIC with excellent gain-flatness for IEEE 802.15.3c WPAN system. The V-band power amplifier was designed using ETRI' $0.12{\mu}m$ PHEMT process. The PHEMT shows a peak transconductance ($G_{m,peak}$) of 500 mS/mm, a threshold voltage of -1.2 V, and a drain saturation current of 49 mA for 2 fingers and $100{\mu}m$ total gate width (2f100) at $V_{ds}$=2 V. The RF characteristics of the PHEMT show a cutoff frequency, $f_T$, of 97 GHz, and a maximum oscillation frequency, $f_{max}$, of 166 GHz. The gains of the each stages of the amplifier were modified to have broadband characteristics of input/output matching for first and fourth stages and get more gains of edge regions of operating frequency range for second and third stages in order to make the gain-flatness of the amplifier excellently for wide band. The performances of the fabricated 60 GHz power amplifier MMIC are operating frequency of $56.25{\sim}62.25\;GHz$, bandwidth of 6 GHz, small signal gain ($S_{21}$) of $16.5{\sim}17.2\;dB$, gain flatness of 0.7 dB, an input reflection coefficient ($S_{11}$) of $-16{\sim}-9\;dB$, output reflection coefficient ($S_{22}$) of $-16{\sim}-4\;dB$ and output power ($P_{out}$) of 13 dBm. The chip size of the amplifier MMIC was $3.7{\times}1.4mm^2$.

• 한국정보통신학회논문지
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• 제21권9호
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• pp.1627-1634
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• 2017

비정질 InGaZnO 박막 두께가 다른 무접합 트랜지스터를 제작하고 두께에 따른 양과 음의 게이트 스트레스 전압 및 빛을 비춘 상태에서 소자 불안정성을 분석하였다. 채널 박막 두께가 얇을수록 게이트 스트레스 및 빛이 인가된 상태에서 문턱전압 및 드레인 전류 변화가 큰 것을 알 수 있었다. 그 원인을 stretched-exponential 모델과 소자 시뮬레이션을 수행하여 설명하였다. 박막이 얇을수록 캐리어 트랩핑 시간이 짧기 때문에 전자나 홀이 빨리 활성화되는 것과 채널 박막의 뒷부분에서 채널의 수직 전계가 증가하여 전자나 홀을 많이 축적할 수 있는 것으로 설명하였다. IGZO 무접합 트랜지스터 제작에서 채널 박막의 두께를 결정할 때 채널 박막 두께가 얇을수록 소자 불안정성이 큰 것을 고려해야 됨을 알 수 있다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.330-332
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• 2009

Highly stable bottom gate thin film transistors(TFTs) with a zinc indium tin oxide(Zn-In-Sn-O:ZITO) channel layer have been fabricated by rf-magnetron co-sputtering using a indium tin oxide(ITO:90/10), a tin oxide and a zinc oxide targets. The ZITO TFT (W/L=$40{\mu}m/20{\mu}m$) has a mobility of 24.6 $cm^2$/V.s, a subthreshold swing of 0.12V/dec., a turn-on voltage of -0.4V and an on/off ratio of >$10^9$. When gate field of $1.8{\times}10^5$ V/cm was applied with source-drain current of $3{\mu}A$ at $60^{\circ}C$, the threshold voltage shift was ~0.18 V after 135 hours. We fabricated AM-OLED driven by highly stable bottom gate Zn-In-Sn-O TFT array.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• 한국정보통신학회논문지
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• 제10권2호
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• pp.303-307
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• 2006

본 논문에서는 게이트길이가 $0.9{\mu}m,\;0.1{\mu}m$를 갖는 p형 SiGe MOSFET에 대한 전기적 특성들을 TCAD 시뮬레이터를 이용하여 연구하였다. 또한 온도 300K와 77K일 때 2개의 캐리어 전송모델(하이드로 다이나믹 모델과 드리프트-확산 모델)을 사용하여 전기적 특성들을 비교 분석하였다. 본 논문에서는 드리프트-확산 모델보다는 하이드로 다이나믹 모델을 사용하였을 때 드레인 전류가 더 많이 흐름을 알 수 있었다. 게이트 길이가 $0.9{\mu}m$일 때 문턱 전압은 온도가 300K, 77K에서 각각 -0.97V와 -1.15V의 값을 가짐을 알수 있었다. 또한 게이트 길이가 $0.1{\mu}m$일 때 문턱전압들은 게이트길이가 $0.9{\mu}m$일 때의 값과 거의 같음을 알 수 있었다.

• E2M - 전기 전자와 첨단 소재
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• 제9권1호
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• 센서학회지
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• 제12권5호
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• pp.218-224
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• 2003

플라즈마, $H_2$와 $H_2$/플라즈마 공정에 의해 수소 처리시킨 n-채널 다결정실리콘 박막트랜지스터(TFT)를 제작하였다. 전압 바이어스 스트레스로 게이트 산화막에 유기된 감지 특성들을 분석하였다. 수소 처리시킨 소자에서 전기적 스트레스 조건에 의해 야기된 인자적 감지 특성들은 드레인전류, 문턱전압(Vth), 문턱전압 아래기울기(S), 그리고 최대 전달 컨덕턴스(Gm) 값을 측정하여 조사하였다. 분석 결과로서, 수소화 처리시킨 n-채널 다결정 실리콘 박막 트랜지스터에서 감지된 열화특성은 다결정실리콘/산화막의 계면과 다결정 실리콘의 그레인 경계에서 실리콘-수소(Si-H) 본드의 해리에 의한 현수 본드의 증가가 원인이 되었다. 게이트 산화막내 트랩의 생성은 채널 영역에서 게이트 산화막 속으로 핫 전자 주입에 의해 야기되었다.