• Title/Summary/Keyword: Drain Work

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A 3.3V, 68% power added efficieny, GaAs power MESFET for mobile digital hand-held phone (3.3V 동작 68% 효율, 디지털 휴대전화기용 고효율 GaAs MESFET 전력소자 특성)

  • 이종남;김해천;문재경;이재진;박형무
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.6
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    • pp.41-50
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    • 1995
  • A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

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Simulation Study on the Breakdown Characteristics of InGaAs/InP Composite Channel MHEMTs with an InP-Etchstop Layer (InP 식각정지층을 갖는 MHEMT 소자의 InGaAs/InP 복합 채널 항복 특성 시뮬레이션)

  • Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.12 no.4
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    • pp.21-25
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    • 2013
  • This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

Effects of Air Drain and Confined Conditions to Infiltration Rate in Unsaturated Soils (불포화 토양에서 공기의 배출/제한이 침투속도에 미치는 영향)

  • Kim, Sangrae;Ki, Jaehong;Kim, Youngjin;Han, Mooyoung
    • Journal of Korean Society of Water and Wastewater
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    • v.22 no.6
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    • pp.681-687
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    • 2008
  • It is well known that the water infiltration rate depends on soil properties such as soil water content, water head, capillary suction, density, hydraulic conductivity, and porosity. However, most of proposed infiltration models assume that the air phase is continuous and in equilibrium with the atmosphere or air compression and air entrapment on infiltration was not considered. This study presents experimental results on unsaturated water infiltration to relate air entrapment and hydraulic conductivity function based on soil air properties. The objectives of this study were to measure change of soil air pressure ahead of wetting front under air drain and air confined condition to find the confined air effect on infiltration rate, to reduce the entrapped air volume related with soil air pressure to increase the soil permeability, and to make a basis of infiltration process model for the purpose of improvement of infiltration rate in the homogeneous soil column. The results of the work show that soil air pressure increases according to increasement of the saturated soil depth rather than the wetting front depth during infiltration process.

General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors

  • Najam, Syed Faraz;Tan, Michael Loong Peng;Yu, Yun Seop
    • Journal of information and communication convergence engineering
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    • v.14 no.2
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    • pp.115-121
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    • 2016
  • Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters Ak and Bk, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (Ids-Vgs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

Analytical Characterization of a Dual-Material Double-Gate Fully-Depleted SOI MOSFET with Pearson-IV type Doping Distribution

  • Kushwaha, Alok;Pandey, Manoj K.;Pandey, Sujata;Gupta, Anil K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.2
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    • pp.110-119
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    • 2007
  • A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

Macro Model of DWFG MOSFET for Analog Application and Design of Operational Amplifier (아날로그 응용을 위한 DWFG MOSFET의 매크로 모델 및 연산증폭기 설계)

  • Ha, Ji-Hoon;Baek, Ki-Ju;Lee, Dae-Hwan;Na, Kee-Yeol;Kim, Yeong-Seuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.8
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    • pp.582-586
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    • 2013
  • In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.

Analysis of Threshold Voltage Roll-Off and Drain Induced Barrier Lowering in Junction-Based and Junctionless Double Gate MOSFET (접합 및 무접합 이중게이트 MOSFET에 대한 문턱전압 이동 및 드레인 유도 장벽 감소 분석)

  • Jung, Hak Kee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.2
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    • pp.104-109
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    • 2019
  • An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

Hot carrier induced device degradation for PD-SOI PMOSFET at elevated temperature (고온에서 PD-SOI PMOSFET의 소자열화)

  • 박원섭;박장우;윤세레나;김정규;박종태
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.719-722
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    • 2003
  • This work investigates the device degradation p-channel PD SOI devices at various applied voltages as well as stress temperatures with respect to Body-Contact SOI (BC-SOI) and Floating-Body SOI (FB-SOI) MOSFETs. It is observed that the drain current degradation at the gate voltage of the maximum gate current is more significant in FB-SOI devices than in BC-SOI devices. For a stress at the gate voltage of the maximum gate current and elevated temperature, it is worth noting that the $V_{PT}$ Will be decreased by the amount of the HEIP plus the temperature effects. For a stress at $V_{GS}$ = $V_{DS}$ . the drain current decreases moderately with stress time at room temperature but it decreases significantly at the elevated temperature due to the negative bias temperature instability.

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Analysis of Quantum Effects Concerning Ultra-thin Gate-all-around Nanowire FET for Sub 14nm Technology

  • Lee, Han-Gyeol;Kim, Seong-Yeon;Park, Jae-Hyeok
    • Proceeding of EDISON Challenge
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    • 2015.03a
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    • pp.357-364
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    • 2015
  • In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.

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Experimental Study on Development for Separation and Reinforcement Geotextiles with Horizontal Wicking Drain Property (수평방향의 위킹 배수 특성을 지닌 분리·보강용 지오텍스타일 개발을 위한 실험적 연구)

  • Kim, Hong-Kwan;Ahn, Min-Soo
    • Journal of the Korean Geosynthetics Society
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    • v.18 no.4
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    • pp.215-224
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    • 2019
  • According to the recent civil engineering construction work site which is a complex process, development of multi-functional geotextiles is required. In this study, the characteristics of five different modified cross-section fiber yarns for the selection of wicking yarns were analyzed and yarns that can achieve target properties were selected. Experimental prototype geotextiles suitable for horizontal wicking drain property and reinforcement was developed and its tensile strength, 2% secant modulus, vertical water permeability, AOS, friction characteristics by the direct shear method, and vertical/horizontal wicking test were analyzed. These tests are conducted to verify the performance of the geotextiles with horizontal wick drain property, separation and reinforcement developed in this study. As a results of the indoor soil box test, it was confirmed that the geotextiles using the wicking yarn sufficiently exhibited the function of discharging excess pore water in the horizontal direction.