• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.107-117
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• 2010

An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction. The model is based on the effective conduction path effect (ECPE) concept of uniformly doped symmetric DG MOSFETs. The effect of channel doping on the subthreshold swing characteristics for non-uniformly doped device has been investigated. The model also includes the effect of various device parameters on the subthreshold swing characteristics of DG MOSFETs. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained by using the commercially available $ATLAS^{TM}$ device simulator. The model is believed to provide a better physical insight and understanding of DG MOSFET devices operating in the subthreshold regime.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.745-748
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• 2014

본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 채널길이에 대한 문턱전압이하 스윙의 변화에 대하여 분석하였다. 문턱전압이하 스윙은 트랜지스터의 디지털특성을 결정하는 중요한 요소로서 채널길이가 감소하면 특성이 저하되는 문제가 나타나고 있다. 이러한 문제를 해결하기 위하여 개발된 DGMOSFET의 문턱전압이하 스윙의 채널길이에 대한 변화를 채널두께, 산화막두께, 상하단 게이트 전압 및 도핑농도 등에 따라 조사하고자 한다. 특히 하단 게이트 구조를 상단과 달리 제작할 수 있는 비대칭 DGMOSFET에 대하여 문턱전압이하 스윙을 분석함으로써 하단 게이트 전압 및 하단 산화막 두께 등에 대하여 자세히 관찰하였다. 문턱전압이하 스윙의 해석학적 모델을 구하기 위하여 포아송방정식에서 해석학적 전위분포모델을 유도하였으며 도핑분포함수는 가우스분포함수를 사용하였다. 결과적으로 문턱전압이하 스윙은 상하단 게이트 전압 및 채널도핑농도 그리고 채널의 크기에 매우 민감하게 변화하고 있다는 것을 알 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.759-762
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• 2014

비대칭 이중게이트(double gate; DG) MOSFET는 단채널 효과를 감소시킬 수 있는 새로운 구조의 트랜지스터이다. 본 연구에서는 비대칭 DGMOSFET의 전도중심에 따른 차단전류를 분석하고자 한다. 전도중심은 채널 내 캐리어의 이동이 발생하는 상단게이트에서의 평균거리로써 상하단 게이트 산화막 두께를 달리 제작할 수 있는 비대칭 DGMOSFET에서 산화막 두께에 따라 변화하는 요소이며 상단 게이트 전압에 따른 차단전류에 영향을 미치고 있다. 전도중심을 구하고 이를 이용하여 상단 게이트 전압에 따른 차단전류를 계산함으로써 전도중심이 차단전류에 미치는 영향을 산화막 두께 및 채널길이 등을 파라미터로 분석할 것이다. 차단전류를 구하기 위하여 포아송방정식으로부터 급수 형태의 해석학적 전위분포를 유도하였다. 결과적으로 전도중심의 위치에 따라 차단전류는 크게 변화하였으며 이에 따라 문턱전압 및 문턱전압이하 스윙이 변화하는 것을 알 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.395-398
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA(240$^{\ast}$320) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1451-1453
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• 2001

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with graded gate and recessed source is proposed. The proposed structure can increase the breakdown voltage by reducing the electric field crowding at the edge of gate. Simulation results by TSUPREM4 and MEDICI have shown that the breakdown voltage of proposed device was found to be 52 V while that of conventional device was 45 V. At the same breakdown voltage of 45 V, the on-resistance of the LDMOS with graded gate and recessed source was 14.4 % lower than that of conventional structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.773-776
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• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.223-226
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• 2003

We propose an improvement method for a $\underline{G}ate$ $\underline{OX}ide(GOX)$ thinning at the edge of $\underline{S}hallow$ $\underline{T}rench$ $\underline{I}solation(STI)$, when STI is adopted to Dual Gate Oxide(DGOX) Process. In the case of SOC(System On-a-Chip), the DGOX process is usually used for realizing both a low and a high voltage parts in one chip. However, it is found that the severe GOX thinning occurs from at STI top edge region and a dent profile exists at the top edge of STI, when conventional DGOX and STI process carried out in high density device chip. In order to overcome this problem, a new DGOX process is tried in this study. And we are able to prevent the GOX thinning by H2 anneal, partially SiN liner skip, and a method which is merged a thick sidewall oxide(S/O) with a SiN pull-back process. Therefore, a good subthreshold characteristics without a double hump is obtained by the prevention of a GOX thinning and a deep dent profile.