• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.213-217
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• 2015

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

• 한국진공학회지
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• 제17권6호
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• pp.566-575
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• 2008

촉매 화학기상증착법을 이용하여 합성된 이중층 탄소나노튜브를 가지고 전계전자 방출원을 제작하여 이들의 신뢰성 있는 전계전자 방출특성을 조사하였다. 합성된 탄소 필라멘트들은 TEM, TGA, 그리고 Raman 분석을 통하여 결함이 없고 순도가 높은 이중층 탄소나노튜브가 합성이 되었음을 확인하였다. 이들 이중층 탄소나노튜브 전계전자 방출원은 이전극 구조에서 낮은 턴-온 전계와 높은 전류밀도의 전계전자 방출 특성을 보여주었고, 균질한 전계방출 패턴과 좋은 전계방출 안정성을 나타내었다.

• 한국전기전자재료학회논문지
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• 제13권11호
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• pp.943-949
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• 2000

In this paper, the single and double heterostructure organic light-emitting devices(OLEDs) were fabricated. The single heterostructure OLED(TYPE 1) is consisted of TPD as a HTL(hole transfer layer) and Alq$_3$as an EML(emitting layer). The double heterostructure OLED(TYPE 2) is consisted of TPD as a HTL, Alq$_3$as an EML and PBD as an ETL(electron transfer layer). The another double heterostructure OLED(TYPE 3) is consisted of TPD as a HTL, PBD as an EML and Alq$_3$as an ETL. We obtained a strong green emission device with maximum EL emission wavelength 500nm in TYPE 3. When the applied voltage was 12V, the emission luminescence was 120.9cd/㎡. The chromaticity index of TYPE 3 was x=0.29, y=0.50. In the characteristic plot of current-voltage, TYPE 3 device was turned on at 6.9V. This voltage was a fairly low turn-on voltage. TYPE 1 and 2 device were turned on at 10V and 8.9V respectively. These types showed no good properties over that of TYPE 3.

• 전력전자학회논문지
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• 제4권6호
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• pp.547-553
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• 1999

본 논문에서는 기존의 12-스텝 인버터에 간단한 보조회로를 추가하여 24-스텝(또는 36-스텝)의 출력파형을 갖는 새로운 방식의 이중접속 멀티스텝 인버터를 제안한다. 제안한 인버터의 보조회로는 두 개의 전압분할용 커패시터, 두 개의 스위칭소자와 저용량의 단권변압기로 구성된다. 이 보조회로의 동작으로 24-스텝의 입·출력 파형을 얻을 수 있으며 한 개의 양방향 스위칭 소자를 추가하면 36-스텝의 파형을 얻게된다. 스위칭 함수를 이용한 전압 및 전류의 분석을 통하여 설계에 필요한 최적의 파라미터를 설정하였다. 제안한 인버터는 PWM방식을 사용할 수 없는 중용량의 SVC등에 적용하면 효과적이다. 본 방식의 타당성을 실험 및 시뮬레이션을 통하여 입증하였다.

• 한국분말재료학회지
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• 제25권6호
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• pp.514-522
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• 2018

Layered-double hydroxide (LDH)-based nanostructures offer the two-fold advantage of being active catalysts with incredibly large specific surface areas. As such, they have been studied extensively over the last decade and applied in roles as diverse as light source, catalyst, energy storage mechanism, absorber, and anion exchanger. They exhibit a unique lamellar structure consisting of a wide variety of combinations of metal cations and various anions, which determine their physical and chemical performances, and make them a popular research topic. Many reviewed papers deal with these unique properties, synthetic methods, and applications. Most of them, however, are focused on the form-factor of nanopowder, as well as on the control of morphologies via one-step synthetic methods. LDH nanostructures need to be easy to control and fabricate on rigid substrates such as metals, semiconductors, oxides, and insulators, to facilitate more viable applications of these nanostructures to various solid-state devices. In this review, we explore ways to grow and control the various LDH nanostructures on rigid substrates.

• 한국수소및신에너지학회논문집
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• 제29권6호
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• pp.627-634
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• 2018

Gallium-based liquid metal, e.g., eutectic gallium-indium (EGaIn), is highly attractive as an electrode material for flexible and stretchable devices. On the liquid metal, oxide layer is spontaneously formed, which has a wide band-gap, and therefore is electrically insulating. In this paper, we fabricate a capacitor based on eutectic gallium-indium (EGaIn) liquid metal and investigate its cyclic voltammetry (CV) behavior. The EGaIn capacitor is composed of two EGaIn electrodes and electrolyte. CV curves reveal that the EGaIn capacitor shows the behavior of electric double-layer capacitors (EDLC), where the oxide layers on the EGaIn electrodes serves as the dielectric layer of EDLC. The oxide thicker than the spontaneously-formed native oxide decreases the capacitance of the EGaIn capacitor, due to increased voltage loss across the oxide layer. The EGaIn capacitor without oxide layer exhibits unstable CV curves during the repeated cycles, where self-repair characteristic of the oxide was observed. Finally, the electrolyte concentration is optimized by comparing the CV curves at various electrolyte concentrations.

• 대한전자공학회논문지
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• 제23권6호
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• pp.758-765
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• 1986

The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.

• 전기전자학회논문지
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• 제27권4호
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• pp.418-424
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• 2023

본 연구에서는 더블게이트 실리콘 나노시트 (SiNS) 피드백 전계효과 트랜지스터(FBFET)의 전기적 특성에 열처리가 미치는 영향을 분석하였다. 1000 초 동안 바이어스 스트레스를 인가했을 때 더블게이트 SiNS FBFET는 inversion layer의 전자에 의한 계면 트랩의 증가로 인해 채널 모드와 무관하게 negative bias stress 보다는 positive bias stress의 영향을 더 많이 받았다. 300 ℃에서 10 분 동안 열처리를 진행한 이후 소자는 원래의 특성을 완전히 회복하였으며 다시 1000 초 동안 바이어스 스트레스를 인가해도 특성이 변하지 않았다.

• Advances in nano research
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• 제16권1호
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• pp.91-109
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• 2024

Carbon nanotubes are drawing wide attention of research communities and several industries due to their versatile capabilities covering mechanical and other multi-physical properties. However, owing to extreme operating conditions of the synthesis process of these nanostructures, they are often imposed with certain inevitable structural deformities such as single vacancy and nanopore defects. These random irregularities limit the intended functionalities of carbon nanotubes severely. In this article, we investigate the mechanical behaviour of double-wall carbon nanotubes (DWCNT) under the influence of arbitrarily distributed single vacancy and nanopore defects in the outer wall, inner wall, and both the walls. Large-scale molecular simulations reveal that the nanopore defects have more detrimental effects on the mechanical behaviour of DWCNTs, while the defects in the inner wall of DWCNTs make the nanostructures more vulnerable to withstand high longitudinal deformation. From a different perspective, to exploit the mechanics of damage for achieving defect-induced shape modulation and region-wise deformation control, we have further explored the localized longitudinal and transverse spatial effects of DWCNT by designing the defects for their regional distribution. The comprehensive numerical results of the present study would lead to the characterization of the critical mechanical properties of DWCNTs under the presence of inevitable intrinsic defects along with the aspect of defect-induced spatial modulation of shapes for prospective applications in a range of nanoelectromechanical systems and devices.

• 한국정밀공학회지
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• 제24권1호
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• pp.64-70
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• 2007

A long-exposing technique (LET) has been conducted to create nanoscale patterns applicable to diverse micro-devices using two-photon polymerization (TPP). By the weakly-polymerized region via the LET, double-layered embossing patterns can be fabricated simply in a single step. The LET makes possible a voxel and its surrounding to be fully grown into more than 500 nm in lateral size and weakly-polymerized region (WPR), respectively. In the WPR. interconnecting ribs between voxels are generated, and they lead to the creation of double-layered dot patterns. Moreover, by controlling the distance between voxels, various shapes of interconnecting rib can be fabricated when the LET is applied. Various embossing patterns were fabricated to evaluate the usefulness of the proposed technique as a novel nanopatterning technique in TPP.