Acknowledgement
This study was partly supported by the Brain Korea 21 Plus Project, a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (2020R1A2C3004538, 2022M3I7A3046571), Samsung Electronics (IO201223-08257-01), and a Korea University Grant.
References
- S. Cristoloveanu, K. H. Lee, H. Park, and M. S. Parihar, "The concept of electrostatic doping and related devices," Solid-State Electronics, vol.155, pp.32-40, 2019. DOI: 10.1016/j.sse.2019.03.017
- H. Kanget al., "Nonvolatile and volatile memory characteristics of a silicon nanowire feedback field-effect transistor with a nitride charge-storage layer," IEEE Transactions on Electron Devices, vol.66, no.8, pp.3342-3348, 2019. DOI: 10.1109/TED.2019.2924961
- A. Z. Badwan, Q. Li, and D. E. Ioannou, "On the nature of the memory mechanism of gated-thyristor dynamic-RAM cells," IEEE Journal of the Electron Devices Society, vol.3, no.6, pp.468-471, 2015. DOI: 10.1109/JEDS.2015.2480377
- S. Cristoloveanuet al., "A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters," Solid-State Electronics, vol.143, pp.10-19, 2018. DOI: 10.1016/j.sse.2017.11.012
- D. Lim, J. Son, K. Cho, and S. Kim, "Quasi-nonvolatile silicon memory device," Advanced Materials Technologies, vol.5, no.12, pp.2000915, 2020. DOI: 10.1002/admt.202000915
- J. Cho, D. Lim, S. Woo, K. Cho, and S. Kim, "Static random access memory characteristics of single-gated feedback field-effect transistors," IEEE Transactions on Electron Devices, vol.66, no.1, pp.413-419, 2018. DOI: 10.1109/TED.2018.2881965
- S. Han, Y. Kim, D. Son, H. W. Baac, S. M. Won, and C. Shin, "Study on memory characteristics of fin-shaped feedback field effect transistor," Semiconductor Science and Technology, vol.37, no.6, pp.065-006, 2022. DOI: 10.1088/1361-6641/ac643e
- Y.-S. Park, S. Woo, D. Lim, K. Cho, and S. Kim, "Integrate-and-fire neuron circuit without external bias voltages," Frontiers in neuroscience, vol.15, pp.644-604, 2021. DOI: 10.3389/fnins.2021.644604
- D. Lim, K. Cho, and S. Kim, "Single silicon neuron device enabling neuronal oscillation and stochastic dynamics," IEEE Electron Device Letters, vol.42, no.5, pp.649-652, 2021. DOI: 10.1109/LED.2021.3063954
- S. Woo and S. Kim, "Neural oscillation of single silicon nanowire neuron device with no external bias voltage," Scientific reports, vol.12, no.1, pp.3516, 2022. DOI: 10.1038/s41598-022-07374-2
- D. Lim and S. Kim, "Polarity control of carrier injection for nanowire feedback field-effect transistors," Nano Research, vol.12, pp.2509-2514, 2019. DOI: 10.1007/s12274-019-2477-6
- T. Kim, D. Lim, J. Son, K. Cho, and S. Kim, "Reconfiguration of operation modes in silicon nanowire field-effect transistors by electrostatic virtual doping," Nanotechnology, vol.33, no.41, pp.415203, 2022. DOI: 10.1088/1361-6528/ac7dae
- M. Kim, Y. Kim, D. Lim, S. Woo, K. Cho, and S. Kim, "Steep switching characteristics of single-gated feedback field-effect transistors," Nanotechnology, vol.28, no.5, pp.055205, 2016. DOI: 10.1088/1361-6528/28/5/055205
- T. Park. et al., "Temperature-Dependent Electrical Characteristics of p-Channel Mode Feedback Field-Effect Transistors," IEEE Access, vol.10, pp.101458-101464, 2022. DOI: 10.1109/ACCESS.2022.3208116
- J. Son, K. Cho, and S. Kim, "Electrical Stability of p-Channel Feedback Field-Effect Transistors Under Bias Stresses," IEEE Access, vol.9, pp.119402-119405, 2021. DOI: 10.1109/ACCESS.2021.3108232
- C. Peng. et al., "Investigation of negative bias temperature instability effect in partially depleted SOI pMOSFET," IEEE Access, vol.8, pp.99037-99046, 2020. DOI: 10.1109/ACCESS.2020.2997463
- S. Navarroet al., "Reliability study of thin-oxide zero-ionization, zero-swing FET 1T-DRAM memory cell," IEEE Electron Device Letters, vol. 40, no.7, pp.1084-1087, 2019. DOI: 10.1109/LED.2019.2915118
- A. Ghetti, "Gate oxide reliability: Physical and computational models," in Predictive simulation of semiconductor processing: status and challenges: Springer, 2004, pp.201-258. DOI:10.1007/978-3-662-09432-7_6
- L. Tsetseris, R. D. Schrimpf, D. M. Fleetwood, R. L. Pease, and S. T. Pantelides, "Common origin for enhanced low-dose-rate sensitivity and bias temperature instability under negative bias," IEEE transactions on nuclear science, vol.52, no.6, pp.2265-2271, 2005. DOI: 10.1109/TNS.2005.860670
- Y. Shin, J. Son, J. Jeon, K. Cho, and S. Kim, "Logic-In-Memory Characteristics of Reconfigurable Feedback Field-Effect Transistors with Double-Gated Structure," Advanced Electronic Materials, pp.2300132, 2023. DOI: 10.1002/aelm.202300132
- P. Samanta, H.-S. Huang, S.-Y. Chen, T.-J. Tzeng, and M.-C. Wang, "Interface trap generation and recovery mechanisms during and after positive bias stress in metal-oxide-semiconductor structures," Applied Physics Letters, vol.100, no.20, 2012. DOI: 10.1063/1.4711216
- L. Tsetseris, X. J. Zhou, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelides, "Hydrogen-related instabilities in MOS devices under bias temperature stress," IEEE Transactions on Device and Materials Reliability, vol.7, no.4, pp.502-508, 2007. DOI: 10.1109/TDMR.2007.910438
- S. Rashkeev, D. Fleetwood, R. Schrimpf, and S. Pantelides, "Effects of hydrogen motion on interface trap formation and annealing," IEEE Transactions on Nuclear Science, vol.51, no.6, pp.3158-3165, 2004. DOI: 10.1109/TNS.2004.839202
- M. L. Reed and J. D. Plummer, "Chemistry of Si-SiO2 interface trap annealing," Journal of applied physics, vol.63, no.12, pp.5776-5793, 1988. DOI 10.1063/1.340317