• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.738-742
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• 2011

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction of channel length. DIBL has to be small with decrease of channel length, but it increases with decrease of channel length due to SCEs. This potential model is used to obtain the change of DIBL for DGMOSFET correlated to channel doping profiles. Also device parameters including channel length, channel thickness, gate oxide thickness and doping intensity have been used to analyze DIBL.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.969-975
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• 2002

Thin film transistors(TFT) were made based on the polycrystalline Si (poly-Si) crystallized by sequential lateral solidification(SLS) method. The electrical characteristics of the devices were analyzed. n-type TFTs did not show a superior characteristics compared to p-type TFTs. We analyzed the causes of the failure by focused ion beam(FIB) analysis and automatic spreading resistance(ASR) measurement, to study the structural integrity and the doping distribution, respectively. FIB showed no structural problems but it revealed a non-intermixed layer in the contact holes between the polysilicon and the aluminum electrode. ASR analyses on poly-Si layer with various doping concentrations and activation temperatures showed that the inadequately doped areas were partially responsible for the inferior behavior of the whole device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Journal of Powder Materials
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• v.9 no.4
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• pp.273-279
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• 2002

In this study, the WC-10 wt.%Co nanopowders doped by grain growth inhibiter were produced by three different methods based on the spray conversion process. Agglomerated powders with homeogenous distribution of alloying elements and with internal particles of about 100-200 nm in diameter were synthesized. The microstructural changes and sintering behavior of hardmetal compacts were compared with doping method and sintering conditions. The microstructure of hardmetals was very sensitive to doping methods of inhibitor. Nanostructured WC-Co hardmetal powder compacts containing TaC/VC doped by chemical method instead of ball-milling shown superior sintering densification, and the microstructure maintained ultrafine scale with rounded WC particles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1069-1074
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.3
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• pp.165-169
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• 2002

Silicon wafer is very important accuracy make use semiconductor device substrate. In this research, for the uniformity dopant density distribution obtained to Neutron Transmutation Doping on make use Si in P Doping study work. In this research. we irradiated neutron on FZ silicon wafers which had high resistivity (1000~2000 ${\Omega}$cm), HANARO reactor was utilized resistivity changes due to observed, the generation of neutron irradiation on point defect analyzed, point defect on resistivity changes inquire into the effect. Before neutron irradiation theoretical due to calculated 5 ${\Omega}$-cm, 20.1 ${\Omega}$-cm for HTS hole and 5 ${\Omega}$-cm, 26.5 ${\Omega}$-cm, 32.5 ${\Omega}$-cm for IP3 hole. After neutron irradiation through SRP measurement the designed resistivities were approached, which were 2.1 H-cm for HTS-1, 7.21 ${\Omega}$-cm for HTS-2, 1.79 ${\Omega}$-cm for IP-1, 6.83 ${\Omega}$-cm for IP-2, 9.23 ${\Omega}$-cm for IP-3, respectively. Also after neutron irradiation resistivity changes due to thermal neutron dependent irradiation hole types free.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1196-1202
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• 2013

This paper have analyzed the change of breakdown voltage for channel doping concentration and device parameters of double gate(DG) MOSFET using two dimensional potential model. The low breakdown voltage becomes the obstacle of power device operation, and breakdown voltage decreases seriously by the short channel effects derived from scaled down device in the case of DGMOSFET. The two dimensional analytical potential distribution derived from Poisson's equation have been used to analyze the breakdown voltage for device parameters such as channel length, channel thickness, gate oxide thickness and channel doping concentration. Resultly, we could observe the breakdown voltage has greatly influenced on device dimensional parameters as well as channel doping concentration, especially the shape of Gaussian function used as channel doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.789-794
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• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.56-59
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• 2000

In this paper, we have made a comparison between secondary ion mass spectroscopy(SIMS) data by the 5kcV-15keV boron implantation and computer simulation results. In order to make electrical activation of implanted carriers, thermal annealing are carried out by RTP method for 30s at 1000$^{\circ}C$ Two dimensional doping concentration distribution from different mask dimensions under inert gas annealing, dry-, and wet-oxidation condition were calculated and simulated with microtec simulator.