• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.225-228
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• 2004

This paper has been studied about UWB(Ulra wide-band)'s LNA(Low Noise Amplifier) and Mixer. The UWB is a new technology that is being pursed for both commercial and military purposes. Direct conversion architectures that convert RF signals have potential to achieve such terminals, because they eliminate the need for non-programmable image-rejection filters and IF channel filters. And this architecture promises better performance in power, size, and cost than existing heterodyne - based receivers. This Receiver architectures combines low-noise amplifier, mixer. And then this paper has designed suitable UWB's LNA and Mixer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.435-438
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• 2002

A design of Ku-band(11.7~12.20Hz) monolithic microwave integrated circuit(MMIC) low noise block(LNB) downconverter using self oscillating mixer (SOM) for direct broadcast satellite(DBS) application is presented The proposed LNB downconverter is composed of low noise amplifier(LNA), image reject filter(IRF), SOM , low pass filter(LPF). The conversion gain is 30dB , VSn is less than 1.7: 1 and overall noise figure is less than 1.2dB.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.174-181
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• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.45-49
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• 2009

본 논문에서는 900Mhz 대역의 UHF RFID에서 직접변환방식의 LNA/Mixer를 설계하였다. 설계된 회로는 3.3V로 동작하며, 0.18um CMOS 공정으로 구현되었다. 본 논문은 높은 self jamming 신호를 극복하기 위해 공통게이트 입력 구조를 사용하였으며, 고이득, 저이득의 두 가지 동작 모드를 갖도록 설계되었다 측정결과, 설계된 LNA/Mixer는 고이득 모드와 저이득 모드에서 각각 4dBm과 11dBm의 입력 p1dB를 갖고, 12dB와 3dB의 변환이득을 갖는다. 또한, 두 가지 모드에서 각각 60mW와 79mW의 전력을 소비하며, 16dB와 20dB의 잡음지수를 갖는다.

• Journal of Electrical Engineering and Technology
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• 제7권1호
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• pp.81-85
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• 2012

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

• 전기학회논문지
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• 제57권7호
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• pp.1235-1240
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• 2008

In this paper, we presented an active RFID system in 2.45GHz range including LNA, Mixer and gain block. And in this work, a link budget model for RFID applications are proposed. We describe the detailed design and implementation of our system. Our components in RFID system has features such as low Noise Figure, reliable energy budget, and standard compliance with ISO 18000-4. Our receiver is effective for development and evaluation of prototype applications because of the flexibility of the design hardware. So, our platform will be suitable for versatile item management applications.

• 한국전자파학회논문지
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• 제14권5호
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• pp.472-478
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• 2003

본 논문에서는 LO 신호의 2차 하모닉 성분을 이용하여 2개의 FET를 cascode 구조로 구성한 near zero If특성을 갖는 하모닉 혼합기를 설계,제작하였다. 호모다인 방식에서 사용되는 혼합기는 DC offset이 가장 심각한 문제이다. 이러한 문제를 해결하기 위해서 단자간 분리도를 좋게 하고 near zero IF를 사용하여 혼합기를 설계하였다. 본 논문에서 구현된 혼합기는 간결한 구조에 비해 LO-RF 단자간 분리도가 우수하다. 설계된 혼합기에서 RF 입력 전력 -30 dBm, LO 입력 전력 6 dBm에 대해, 변환이득은 6.7 dB, 잡음지수는 8.4 dB, LO-RF 단자간 분리도는 31.5 dB, IIP3는 -1.9 dBm, IIP2는 -2.8 dBm이다.

• ETRI Journal
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• 제29권4호
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.617-618
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• 2006

A CMOS quadrature Up-converter for a direct-conversion receiver of 5.15-5.825GHz wireless LAN is described. The Up-converter consists of two sub-harmonic mixers, for I and Q channels, and an LO generation network. In order to decrease the number of inductor, I and Q path are merged. The simulation results including all the parasitics show -17.3dB conversion gain at center and -8 dBv oIP3 while consuming 22.968mW under 1.8V supply. The quadrature Up-converter is under fabrication with the other transmitter blocks in a $0.18{\mu}m$ CMOS technology.