• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• Fire Science and Engineering
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• v.29 no.6
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• pp.98-108
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• 2015

An integrated command system is critical for the safety of firefighters and effective work in the headquarters of a special disaster areas such as natural disaster or large man-made hazard. The integrated command system requires environmental information such as temperature, humidity, and $CO_2$ levels, as well as personal physical information such as pulse and air respirator levels. An Analog to Digital Converter (ADC) chip converts sensed information into digital signals, and a Micro Controller Unit (MCU) transmits the digital signals to a transmission board using serial communication through a Serial Peripheral Interface (SPI). The digital signals are saved in a transmission board and transmitted to the integrated command system by a Radio Frequency (RF) unit. The location of fire-fighters in a building are determined using a gyro sensor and an inertial sensor. The collected information is applied to the integrated command system for firefighter safety and to ensure that they can effectively carry out their duties. Tthis study theoretically and experimentally investigated the technologies of RF transmission, indoor position, and an integrated command system that supports decision making using the transmitted information.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.10-17
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• 1995

this thesis proposes a new echo canceller that can be used in a fulll-duplex digital subscriber loopmodem. The modem suffers from nonlinear distortion such as transmitted pulse asymmetry, saturation in transformers, and nonlinearity of data converters. The proposed nonlinear echo canceller can compensate the nolinear distortion by using a nonlinear digital filter based on canonical pieceewise-linear (CPWL) function. Numerical results based on computer simulation are given in this paper. It is shown that the convergence characteristics depend on the initial values of weights of linear filters with absoluters and that the nonlinearity in digital-to-analog(D/A) converter can be compensated by a relatively small number linear filters with absoluters. It is also shown that the proposed algorithm has a faster convergence rate in comparison with Voterra algorithm.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1197-1200
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• 2003

This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.89-92
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• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.48-55
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• 2006

This paper describes the antenna based GPS anti-jamming technology called CRPA(Controlled Reception Pattern Antenna), which used $2{\times}2$ array elements. In this system, the main functions are the antenna complex weight control and the GPS digital I/Q VM(Vector Modulator). To update the VM's I/Q complex weights, the PC based DAC(Digital to Analog Converter) module was also used and the two analog output voltages were applied to the $2{\times}2$ array elements to synthesize the null pattern. In the study, we also simulated the $2{\times}2$ GPS array null patterns to compare the null depth with experimental results. The VM was also modified at the frequency of 1.575GHz for the GPS L1 and controlled by the PC based VM software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12C
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• pp.1131-1137
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• 2009

In this paper, a resource management technique for digital duplexing (DD) systems using orthogonal frequency division multiple access (OFDMA) is proposed. The proposed technique can reduce the dynamic range of the signal received at the subscriber station (SS) and minimize the effects of inter-symbol interference (ISI) and inter-carrier interference (ICI) due to the time difference of arrival (TDoA) without using a cyclic suffix. It is shown by computer simulation that the proposed technique can reduce the number of bits for an analog-to-digital converter (ADC) and increase the signal-to-interference and noise ratio (SINR) significantly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.961-965
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• 2006

Design Up/Down converters which use Digital IF( Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the position If frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.