• 제목/요약/키워드: Digital Logic

검색결과 673건 처리시간 0.02초

DIGITAL LOGIC INTERFACE구현 (An Implementation of PC based digital logic interface)

  • 민진경;오훈;조현섭;유인호;김희숙
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2004년도 하계학술대회 논문집 D
    • /
    • pp.2487-2488
    • /
    • 2004
  • In suite or the presence or various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

  • PDF

대역 제한된 직접 시퀀스 CDMA 확산 대역 신호를 위한 전 디지탈 부호 획득 및 추적 루우프 FPGA 구현 (A FPGA implementation of a full-digital code acquisition/Tracking Loop for the CDMA direct-sequence spread-spectrum signals)

  • 김진천;박홍준;임형수;전경훈
    • 전자공학회논문지A
    • /
    • 제33A권5호
    • /
    • pp.165-171
    • /
    • 1996
  • A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

  • PDF

Digital Relaying Algorithm for Power Transformer Protection using Fuzzy Logic Approach

  • Park, Chul-Won;Shin, Myong-Chul
    • KIEE International Transactions on Power Engineering
    • /
    • 제2A권4호
    • /
    • pp.153-159
    • /
    • 2002
  • Power transformer protective relay should block the tripping during magnetizing inrush and rapidly operate the tripping during internal faults. Recently, the frequency environment of power system has been made more complicated and the quantity of 2nd frequency component in inrush state has been decreased because of the improvement of core steel. And then, traditional approaches will likely be maloperate in the case of magnetizing inrush with low second harmonic component and internal faults with high second harmonic component. This paper proposes a new relaying algorithm to enhance the fault detection sensitivities of conventional techniques by using a fuzzy logic approach. The proposed fuzzy based relaying algorithm consists of flux-differential current derivative curve, harmonic restraint, and percentage differential characteristic curve. The proposed relaying was tested with relaying signals obtained from EMTP simulation package and showed a fast and accurate trip operation.

PC기반의 DIGITAL LOGIC INTERFACE구현 (An Implementation of PC based digital logic Interface)

  • 조현섭;송용화;류병식;김수용;김희숙
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2000년도 하계학술대회 논문집 D
    • /
    • pp.2802-2803
    • /
    • 2000
  • In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small Quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

  • PDF

범용 CMOS 공정을 사용한 DTMOS 슈미트 트리거 로직의 구현을 통한 EM Immunity 향상 검증 (DTMOS Schmitt Trigger Logic Performance Validation Using Standard CMOS Process for EM Immunity Enhancement)

  • 박상혁;김소영
    • 한국전자파학회논문지
    • /
    • 제27권10호
    • /
    • pp.917-925
    • /
    • 2016
  • 슈미트 트리거 로직(Schmitt Trigger Logic)은 디지털 회로의 노이즈에 대한 내성을 향상시키기 위해 히스테리시스 특성을 보이는 게이트를 제안한 설계 방법이다. 슈미트 트리거 특성을 보이는 설계 방법 중 최근에 제안된 substrate bias를 조정하여 구현하는 Dynamic Threshold voltage MOS(DTMOS) 방법을 사용할 경우, 게이트 수를 늘이지 않고 내성을 향상 시킬 수 있는 설계방법이나, 범용 CMOS 공정에서 구현하여 시뮬레이션으로 예상하는 성능을 얻을 수 있는지는 검증되지 않았다. 본 연구에서는 $0.18{\mu}m$ CMOS 공정에서 DTMOS 설계 방법을 구현하여 히스테리시스 특성을 측정하여 검증하였다. DTMOS 슈미트 트리거 버퍼, 인버터, 낸드, 노어 게이트 및 간단한 디지털 로직 회로를 제작하였으며, 히스테리시스 특성, 전력 소모, 딜레이 등의 특성들을 관찰하고, 일반적인 CMOS 게이트로 구현된 회로와 비교하였다. 노이즈에 대한 내성이 향상되는 것을 Direct Power Injection(DPI) 실험을 통해 확인하였다. 본 논문을 통해 제작된 DTMOS 슈미트 트리거 로직은 10 M~1 GHz 영역에서 전자파 내성이 향상된 것을 확인할 수 있었다.

FPGA를 이용한 디지털 계측 시스템의 설계 및 구현 (Implementation and Design of Digital Instruments System using FPGA)

  • 최현준;장석우
    • 디지털산업정보학회논문지
    • /
    • 제9권2호
    • /
    • pp.55-61
    • /
    • 2013
  • A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

QPSK변조기법을 위한 Digital 수신기의 심볼동기 알고리즘 성능평가 (Performance Evaluation of Symbol Timing Algorithm for QPSK Modulation Technique in Digital Receiver)

  • 송재철;고성찬;최형진
    • 한국통신학회논문지
    • /
    • 제17권11호
    • /
    • pp.1299-1310
    • /
    • 1992
  • 최근에, 디지탈 데이터 전송을 위한 수신기 타이밍 검출 회로의 디지탈화에 관한 관심이 점점 증가하고 있다. 타이밍 검출 회로의 디지탈화의 결과로 인하여, 타이밍 에러 검출을 위한 새로운 디지탈 알고리즘이 필요하게 된다. 본 논문에서는, 직접 QPSK변조 기법에 적용할 수 있는 Angular Form(AF) Algorithm을 제시하였다. AF Algorithm은 기본적으로 복조된 각 (Detected Angle)과 천이논리표 (Transition Logic Table)등의 개념을 근거로 하여 개발되었다. Gaussian과 Impulsive 잡음을 모델링하여, 이들 두 잡음환경하에서 Monte-Carlo 시뮬레이션을 통하여 알고리즘 성능평가를 하였다. 성능평가 결과, AF Algorithm이 Gardner Algorithm보다 BER, RMS Jitter, S-curve등에서 성능이 개선됨을 알 수 있었다.

  • PDF

고속 프로그램형 논리 제어기 구현을 위한 래더 다이어그램 해석 방법 (A Translation Method of Ladder Diagram for High-Speed Programmable Logic Controller)

  • 김형석;장래혁;권욱현
    • 제어로봇시스템학회논문지
    • /
    • 제5권1호
    • /
    • pp.33-38
    • /
    • 1999
  • This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

  • PDF

A Study on Counter Design using Sequential Systems based on Synchronous Techniques

  • Park, Chun-Myoung
    • Journal of information and communication convergence engineering
    • /
    • 제8권4호
    • /
    • pp.421-426
    • /
    • 2010
  • This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

온라인 설계 맵핑을 이용한 웹 기반 디지털 논리 회로 가상 실험 시스템의 구현 (Implementation of a Web-based Virtual Laboratory System for Digital Logic Circuits Using Online Schematic Mapping)

  • 김동식;서삼준
    • 제어로봇시스템학회논문지
    • /
    • 제11권6호
    • /
    • pp.558-563
    • /
    • 2005
  • In this paper, we implemented a web-based virtual laboratory system(VLab system) with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since the proposed VLab system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, the VLab system is designed to increase the learning and teaching efficiencies of both the learners and the educators, respectively. The learners will be able to achieve high teaming standard and the educators save their time and labor. The virtual experiments on our VLab system are performed according to the following procedure: (1) Circuit composition on the virtual bread board (2). Applying input voltage (3) Output measurements (4) Checkout of experiment results. Furthermore, the circuit composition on the virtual bread board and its corresponding online schematic diagram are displayed together on the VLab system for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.