Browse > Article
http://dx.doi.org/10.6109/jicce.2010.8.4.421

A Study on Counter Design using Sequential Systems based on Synchronous Techniques  

Park, Chun-Myoung (Department of Computer Engineering, Chungju National University)
Abstract
This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.
Keywords
sequential logic systems; synchronous techniques; switching algebra; next-state function; flip-flop excitation; counter design;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Thurman A. Irving, Sajjan G.Shiva and H. Troy Nagle,"Flip-Flops for Multiple-Valued logic," IEEE Trans Compt.,vol.c-25, pp.237-246,Mar.1976.   DOI   ScienceOn
2 Anthony S. Wojiok and Kwang-Ya Fang, "On the design of threevalued asynchronous modules," IEEE Trans. Compt., vol. C-29,pp.889-898, Oct.1980.   DOI   ScienceOn
3 L.P. Maguire, T.M.McGinnity and L.J. McDaid,"From a Fuzzy Flip-Flop to a MVL Flip-Flop," The 29th IEEE ISMVL, Freiburgim Breisgau, Germany, pp.294-299, 20-22 May, 1999.
4 R. Drechsler, M. Keim and B. Becker,"Fault Simulation in Sequential Multi-valued Logic networks," The 27th IEEE ismvl , NOVA SCOTIA, CANADA, .pp.145-150, 28-30 May, 1997.
5 D.Lee, A.Abuda Gaffar, O.Mencer, and W.Luk,"Optimizing hardware function evaluation," IEEE Trans. Comput. pp.1520-1531, vol.54, Dec. 2005.   DOI   ScienceOn
6 R. sastry and Ranganathan,"A VLSI Architecture for Approximate Tree Matching," IEEE Trans. Comput., vol.47, no.3, pp.346-352, Mar. 1988.
7 K.J.Lin, C.W.Kuo and C.S.Lin,"Synthesis of hazard-free asynchronous circuits based on characteristic Graph," IEEE Trans. Copmut., vol.46, no.11, pp. 1246-1263, Nov. 1987.
8 I. Pomeranz and S.M.reddy,"Test Generation for multiple State- Table Faults in Finite-State Machines," IEEE Trans. Comput., vol.45, no.7, pp.783-794,Jul. 1987.
9 David Green, Modern Logic Design, Addison-Wesley Publishing Company, 1986.
10 D.Lee,A.A. Gaffar, O.Mencer, and W.Luk,"Optimization Hardware Function Evaluation," IEEE Trans. Comput., vol.54, No.12, pp.1520-1531, Dec., 2005.   DOI   ScienceOn
11 S.Mitra, N.R.Saxena, and E.J.McCluskey,"Efficient Design diversity Estimation for Combinational Circuits," IEEE Trans. on Computers, pp.1483-1492, Vol.53, No.11, Nov. 2004.   DOI   ScienceOn