• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2487-2488
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• 2004

In suite or the presence or various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

• KIEE International Transactions on Power Engineering
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• v.2A no.4
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• pp.153-159
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• 2002

Power transformer protective relay should block the tripping during magnetizing inrush and rapidly operate the tripping during internal faults. Recently, the frequency environment of power system has been made more complicated and the quantity of 2nd frequency component in inrush state has been decreased because of the improvement of core steel. And then, traditional approaches will likely be maloperate in the case of magnetizing inrush with low second harmonic component and internal faults with high second harmonic component. This paper proposes a new relaying algorithm to enhance the fault detection sensitivities of conventional techniques by using a fuzzy logic approach. The proposed fuzzy based relaying algorithm consists of flux-differential current derivative curve, harmonic restraint, and percentage differential characteristic curve. The proposed relaying was tested with relaying signals obtained from EMTP simulation package and showed a fast and accurate trip operation.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2802-2803
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• 2000

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small Quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.11
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• pp.1299-1310
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• 1992

Recently, digital realizations of timing recovery circuits for digital data transmission are of growing interest. As a result of digital realization of timing recovery circuits, new digital algorithms for timing error detection are required. In this paper, we present a new digital Angular Form(AF) algorithm which can be directly applied to QPSK modulation technique. AF algorithm is basically developed on the concepts of detected angle form and transition logic table. We evaluated the performance of this algorithm by Monte-Carlo simulation method under Gaussian and Impulsive noise environments. From the performance evaluation result, we show that the performance of AF Algorithm is better than that of Gardner in BER, RMS jitter, S-curve.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.33-38
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• 1999

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.421-426
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• 2010

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.6
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• pp.558-563
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• 2005

In this paper, we implemented a web-based virtual laboratory system(VLab system) with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since the proposed VLab system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, the VLab system is designed to increase the learning and teaching efficiencies of both the learners and the educators, respectively. The learners will be able to achieve high teaming standard and the educators save their time and labor. The virtual experiments on our VLab system are performed according to the following procedure: (1) Circuit composition on the virtual bread board (2). Applying input voltage (3) Output measurements (4) Checkout of experiment results. Furthermore, the circuit composition on the virtual bread board and its corresponding online schematic diagram are displayed together on the VLab system for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.