• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1543-1548
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• 2009

In this paper, a high speed code synchronization circuit is proposed. for fast code synchronization, matched filler method is used for initial code acquisition with two channel correlators. Particular frequency patterns of the limited number having the information about PN code start time are composed and transmitted repeatedly to increase the probability of accurate initial synchronization. And digital frequency synthesizer is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.951-954
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• 1999

A direct digital frequency synthesizer is designed in full custom method using 0.65${\mu}{\textrm}{m}$ CMOS n-well technology The chip provides the capability of the parallel operation using up to 4 chips with an operation frequency of 440MHz. The generated waveform can be modulated by various modulation techniques such as QPSK, 256 . 64. 32 . 16 QAM and FM.

• 한국ITS학회:학술대회논문집
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• 2004.11a
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• pp.236-240
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• 2004

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1243-1250
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• 2014

In this paper, a wideband DDS module covering the frequency range from 0.5 to 1.1 GHz was designed and fabricated. The clock frequency of the DDS was selected 2.4 GHz in order for 600 MHz output bandwidth. Multiple spurious cancelling signals having same amplitude and $180^{\circ}$ phase difference compared to the spurious were created at the additional path and added to the output signal within DDS for the spurious performance improvement. The fabricated DDS module showed better spurious performance than the commercial DDS one more than 10 dB and frequency tuning time was 340 ns below.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.27-35
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• 2016

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.2
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• pp.168-180
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• 1992

Commumication technology has been continuously developed to overcome the distance and time for the transmission of information to the human society. Wireless mobile communication, which had been used mostly in the military and police is widely used these days for enterprise and individuals. Therefore the domestic usage of the advanced mobile phone service are progressively gaining wide popularity. The modulation techniques used usually in mobile communications were the analog techniques such as AM and FM, but they are getting replaced by the digital techniques, However, the major disadvantage of the digital communications is the increase of the transmission bandwidth. Therefore, it is very important to use efficiently the limited frequency bandwidth. The domestic research and development on the subject seems quite limited and in order to establish the technology of the digital mobile communications. This thesis presents the design of the frequency hopping synthesizer providing 124 channels with a channel spcing of 200KHz. VCD used in the synthesizer employs a semi-rigid cable for higher purity of signal spectrum, and a hybrid pgase detector is realized with a sample hold phase detector in conjuction with a tri-state phase detedctor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1179-1182
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• 2016

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. This method use the sine-linear phase difference method and differential PCM. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine-linear phase difference is saved by the ROM1 of the $2^N$ sample period. The ROM2 save the difference between the original sine-linear phase difference value and the saved sample value of the ROM1. The ROM compression ratio of 37% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.