• Progress in Superconductivity and Cryogenics
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• v.8 no.1
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.378-385
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• 2008

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a $0.25{\mu}m$ pure digital CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.57-63
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• 1998

This paper describes a CMOS digital-to-analog converter to apply a newly-developed digital-to-analog conversion algorithm. The CMOS digital-to-analog converter has been designed by using 1.2$\mu\textrm{m}$ MOSIS SCMOS parameter and simulated for the performance. The simulated results have shown that the digital-to-analog converter has 200MHz of the maximum conversion rate, 7.41mW of the DC power consumption, and ${\pm}$0.08LSB of INL and ${\pm}$0.098LSB of DNL in 8-b.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.970-973
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• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

• Imaging Science in Dentistry
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• v.34 no.1
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• pp.1-5
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• 2004

Purpose: To evaluate the diagnostic accuracy of occlusal and proximal caries detection using CCD, CMOS, PSP and film system. Materials and Methods : 32 occlusal and 30 proximal tooth surfaces were radiographed under standardized conditions using 3 digital systems; CCD (CDX-2000HQ, Biomedysis Co., Seoul, Korea), CMOS (Schick, Schick Inc., Long Island, USA), PSP (Digora/sup (R)/FMX, Orion Co./Soredex, Helsinki, Finland) and I film system (Kodak Insight, Eastman Kodak, Rochester, USA). 5 observers examined the radiographs for occlusal and proximal caries using a 5-point confidence scale. The presence of caries was validated histologically and radiographically. Diagnostic accuracy was evaluated using ROC curve areas (Az). Results: Analysis using ROC curves revealed the area under each curve which indicated a diagnostic accuracy. For occlusal caries, Kodak Insight film had an Az of 0.765, CCD one of 0.730, CMOS one of 0.742 and PSP one of 0.735. For proximal caries, Kodak Insight film had an Az of 0.833, CCD one of 0.832, CMOS one of 0.828 and PSP one of 0.868. No statistically significant difference was noted between any of the imaging modalities. Conclusion: CCD, CMOS, PSP and film performed equally well in the detection of occlusal and proximal dental caries. CCD, CMOS and PSP-based digital images provided a level of diagnostic performance comparable to Kodak Insight film.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.652-657
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• 1987

This paper describes an application of CMOS Gate Array Integrated Cricuits to the implementation of three functional units: A Multiplexer, Time Switch, and Demultiplexer in the Switching Network and Digital Line Concentrator of TDX-1 system, which is a fully digital time division electronic switching system in Korea. The application of CMOS Gate Array Integrated Circuits significantly improves the overall system performance in terms of power consumption, cost, size, reliability, and timing margin, etc.

• Broadcasting and Media Magazine
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• v.5 no.1
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• pp.59-71
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• 2000

This paper presents a survey of the CMOs-based image sensor and its applications to various real field digital camera. CMOS image sensor, called active pixel sensor (APS), has many interesting properties such ash I회 sensitivity, high speed readout, random access and lower power consumption when it is compared with CCd. this paper also addresses the state-of-the-art of CMOS image sensor, and gives some examples of its application to digital camera and special-purpose cameras. with the advancement of semiconductor technology, CMOS image sensor is a future technology for imaging system, and will be widely used in the filed of image capturing for consumer electronics and scientific measurements.