• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.928-931
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• 2003

This paper presents a digit-serial/parallel multiplier for finite fields GF(2m). The hardware requirements of the implemented multiplier are less than those of the existing multiplier of the same class, while processing time and area complexity. The implemented multiplier possesses the features of regularity and modularity. Thus, it is well suited to VLSI implementation. If the implemented digit-serial multiplier chooses the digit size D appropriately, it can meet the throughput requirement of a certain application with minimum hardware. The multipliers and squarers analyzed in this paper can be used efficiently for crypto processor in Elliptic Curve Cryptosystem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.115-124
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• 2015

In this paper, the method which improves the performance of a serial decimal multiplier, and the method which operates multiple-digit simultaneously are proposed. The proposed serial decimal multiplier reduces the delay by removing encoding module that generates 2X, 4X multiples, and by generating partial product using shift operation. Also, this multiplier reduces the number of operations using multiple-digit operation. In order to estimate the performance of the proposed multiplier, we synthesized the proposed multiplier with design compiler with SMIC 110nm CMOS library. Synthesis results show that the area of the proposed serial decimal multiplier is increased by 4%, but the delay is reduced by 5% compared to existing serial decimal multiplier. In addition, the trade off between area and latency with respect to the number of concurrent operations in the proposed multiple-digit multiplier is confirmed.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.337-340
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• 2001

In this Paper, 3 digit-Serial multilier With 3 digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. We give a design example for the irreducible trinomials $x^{193}$＋ $x^{15＋1}$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The measured results show that the proposed multiplier is 0.3 times smaller than the bit-serial LFSR multiplier..

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.23-30
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• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.892-897
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• 2008

In this paper, a new architecture for digit-parallel/bit-serial GF$(2^m)$ multiplier with low latency is proposed. The proposed multiplier operates in polynomial basis of GF$(2^m)$ and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.140-143
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• 2000

소형화와 안전성에서 보다 더 진보된 ECC( Elliptic Curve Cryptography) 암호화 알고리즘의 하드웨어적 구현을 제안한다. Basis는 VLSI 구현에 적합한 standard basis이며 m=193 ECC 승산기 회로를 설계하였다. Bit-Parallel 구조를 바탕으로 Digit-Serial/Bit-Parallel 방법으로 구현하였다. 제안된 구조는 VHDL 및 SYNOPSYS로 검증되었다.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.