Design of Digit-serial Circuits for Cryptography Module on Smart cards

스마트카드의 암호화모듈 구현에 적합한 Digit-Serial 유한체 연산기 설계

In this Paper, 3 digit-Serial multilier With 3 digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. We give a design example for the irreducible trinomials $x^{193}$＋ $x^{15＋1}$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The measured results show that the proposed multiplier is 0.3 times smaller than the bit-serial LFSR multiplier..