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Low Complexity Digit-Parallel/Bit-Serial Polynomial Basis Multiplier  

Cho, Yong-Suk (영동대학교 정보통신사이버경찰학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.35, no.4C, 2010 , pp. 337-342 More about this Journal
Abstract
In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.
Keywords
Finite fields; Galois fields; Multiplier; Error Correcting Codes; Cryptography;
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Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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