Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of Serial Decimal Multiplier using Simultaneous Multiple-digit Operations

동시연산 다중 digit을 이용한 직렬 십진 곱셈기의 설계

  • Received : 2014.12.12
  • Accepted : 2015.04.01
  • Published : 2015.04.25
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Abstract

In this paper, the method which improves the performance of a serial decimal multiplier, and the method which operates multiple-digit simultaneously are proposed. The proposed serial decimal multiplier reduces the delay by removing encoding module that generates 2X, 4X multiples, and by generating partial product using shift operation. Also, this multiplier reduces the number of operations using multiple-digit operation. In order to estimate the performance of the proposed multiplier, we synthesized the proposed multiplier with design compiler with SMIC 110nm CMOS library. Synthesis results show that the area of the proposed serial decimal multiplier is increased by 4%, but the delay is reduced by 5% compared to existing serial decimal multiplier. In addition, the trade off between area and latency with respect to the number of concurrent operations in the proposed multiple-digit multiplier is confirmed.

본 논문에서는 직렬 십진 곱셈기의 성능을 향상시키는 방안을 제안하고 다중 digit을 동시에 연산하는 방안을 제안한다. 제안하는 직렬 십진 곱셈기는 부분 곱 생성단계의 2배수, 4배수를 생성하기 위한 인코딩 모듈을 없애고 쉬프트 연산만으로 부분 곱을 생성해 지연시간을 감소시킨다. 또한 다중 digit 연산을 이용해 연산의 횟수를 줄인다. 제안하는 직렬 십진 곱셈기의 성능을 평가하기 위해서 Synopsys사의 Design Compiler를 이용하여 SMIC사의 110nm CMOS 공정 라이브러리로 합성하였다. 그 결과 제안한 곱셈기는 기존의 직렬 십진 곱셈기와 비교해 전체 면적은 4% 증가하였지만, 전체 지연시간은 5% 감소함을 보였다. 또한 동시 연산 수가 증가함에 따른 제안한 다중 digit 곱셈기의 면적과 지연시간의 trade-off를 확인하였다.

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References

  1. H. A. H. Fahmy, M. Y. Hassan, Y. Farouk, and R. R. Eissa, "Decimal Floating Point for future processors," IEEE International Conference Microelectronics(ICM '09), pp. 443-446, Dec. 2010.
  2. H. A. H. Fahmy, R. Raafat, A. M. Abdel-Majeed, R Samy, and Y. Farouk, "Energy and Delay Improvement via Decimal Floating Point Units," In proceedings of 19th IEEE International symposium Computer Arithmetic (ARITH '09), pp. 221-224, Jun 2009.
  3. IEEE, IEEE 754 Standard for Binary Floating-Point Arithmetic, 1985.
  4. IEEE, IEEE 754-2008 Standard for Floating-Point Arithmetic, 2008.
  5. C. Coulston and V. Dave, "Addition of BCD Digits using Non-Standard Codes," 22nd International Conference, pp. 148-152, Feb. 2012.
  6. J. Ghassem and P. Behrooz "Constant-time addition with hybrid-redundant numbers: theory and implementations," Integration, the VLSI Journal, Vol. 41, no. 1, pp. 49-64, Jan. 2008. https://doi.org/10.1016/j.vlsi.2007.01.002
  7. M. A. Erle, E. M. Schwarz, and M. J. Schulte, "Decimal multiplication with efficient partial product generation," In proceedings of 17th IEEE symposium on computer arithmetic, pp. 21-28, Jun. 2005.
  8. L. Han, A. Kaivani, and S. B. Ko, "Area Efficient Sequential Decimal Fixed-point Multiplier," Journal of Signal Processing Systems, Vol. 75, no. 1, pp. 39-46, Apr. 2013. https://doi.org/10.1007/s11265-013-0795-6
  9. L. Han and S. B. Ko, "High speed parallel decimal multiplication with redundant internal encodings", IEEE Transactions on Computers, Vol. 62, no. 5, pp. 956-968, May. 2013. https://doi.org/10.1109/TC.2012.35
  10. I. K. Hwang, K. H. Kim, W. O. Yoon, and S. B. Choi, "Design of Parallel Decimal Multiplier using Limited Range of Signed-Digit Number Encoding," Journal of The Institute of Electronics Engineers of korea, Vol. 50, no. 3, pp. 50-58, Mar. 2013.