• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.41-46
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• 2012

A quadrature voltage controlled oscillator(QVCO) for X-band is presented in this paper. The QVCO has fabricated in Charted $0.13{\mu}m$ CMOS process. The QVCO consists of two cross-coupled differential VCO and two differential buffers. The QVCO is controlled by 4 bit of capacitor bank and control voltage of varactor. To have a linear quality factor of varactors, voltage biases of varactors are difference. The QVCO generates frequency tuning range from 6.591 GHz to 8.012 GHz. The phase noise is -101.04 dBc/Hz at 1MHz Offset when output frequency is 7.150 GHz. The supply voltage is 1.5 V and core current 6.5-8.5 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.86-94
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• 2009

An idea to improve the performance of error correction with the amplification of input symbol errors is proposed to ease the mismatching problem which occurs in the hardware implementation of the differential analog PRML decoder. The differential analog PRML decoder is the decoder with two blocks of trellis diagram one of which is without branches of "0" and the other one is without the branches of "1". Decoding is performed by comparing the outputs of two blocks. The decoding error is likely to occur when the difference of two outputs is very small and the hardware implementation is not precise due to mismatching. The proposed idea is to increase the discrimination margin for the output "0" and "1" by amplifying the symbol error while the larger path metrics are saturated. To show the performance improvement of decoding with the proposed idea, simulation results are included

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.7
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• pp.258-264
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• 2018

This paper presents application of a differential search (DS) meta-heuristic optimization algorithm for optimal operation of a micro grid system. The DS algorithm simulates the Brownian-like random-walk movement used by an organism to migrate. The micro grid system consists of a wind turbine, a diesel generator, a fuel cell, and a photovoltaic system. The wind turbine generator is modeled by considering the characteristics of variable output. Optimization is aimed at minimizing the cost function of the system, including fuel costs and maximizing fuel efficiency to generate electric power. The simulation was applied to a micro grid system only. This study applies the DS algorithm with excellence and efficiency in terms of coding simplicity, fast convergence speed, and accuracy in the optimal operation of micro grids based on renewable energy resources, and we compared its optimum value to other algorithms to prove its superiority.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.128-135
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• 2015

In this study, we develop the very short-term precipitation forecasting model as well as classifier based on polynomial radial basis function neural networks by using AWS(Automatic Weather Station) and KLAPS(Korea Local Analysis and Prediction System) meteorological data. The polynomial-based radial basis function neural networks is designed to realize precipitation forecasting model as well as classifier. The structure of the proposed RBFNNs consists of three modules such as condition, conclusion, and inference phase. The input space of the condition phase is divided by using Fuzzy C-means(FCM) and the local area of the conclusion phase is represented as four types of polynomial functions. The coefficients of connection weights are estimated by weighted least square estimation(WLSE) for modeling as well as least square estimation(LSE) method for classifier. The final output of the inference phase is obtained through fuzzy inference method. The essential parameters of the proposed model and classifier such ad input variable, polynomial order type, the number of rules, and fuzzification coefficient are optimized by means of Particle Swarm Optimization(PSO) and Differential Evolution(DE). The performance of the proposed precipitation forecasting system is evaluated by using KLAPS meteorological data.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.