Input Error Amplification for the Ease of Mismatching Problem in the Analog PRML Decoder Implementation

아날로그 PRML 디코딩 회로 구현 시의 미스 매칭 문제 완화를 위한 입력 심볼 에러 값 증폭

  • Yang, Chang-Ju (Electronics and Information Department, Chonbuk National University) ;
  • Sah, Maheswar (Electronics and Information Department, Chonbuk National University) ;
  • Kim, Hyong-Suk (Electronics and Information Department, Chonbuk National University)
  • Published : 2009.08.25

Abstract

An idea to improve the performance of error correction with the amplification of input symbol errors is proposed to ease the mismatching problem which occurs in the hardware implementation of the differential analog PRML decoder. The differential analog PRML decoder is the decoder with two blocks of trellis diagram one of which is without branches of "0" and the other one is without the branches of "1". Decoding is performed by comparing the outputs of two blocks. The decoding error is likely to occur when the difference of two outputs is very small and the hardware implementation is not precise due to mismatching. The proposed idea is to increase the discrimination margin for the output "0" and "1" by amplifying the symbol error while the larger path metrics are saturated. To show the performance improvement of decoding with the proposed idea, simulation results are included

차동형 아날로그 PRML 디코더의 하드웨어 구현 시에 발생하는 mismatching 문제를 해결하기 위해서 입력 심볼 에러를 증폭함으로써 에러 정정 효과를 향상시키는 방법을 제안하였다. 차동형 아날로그 PRML 비터비 디코더는 축약된 길이만큼의 트렐리스 다이아그램 회로를 2 개 구성하고, 그 중 한 회로는 0에 해당하는 가지들을 절단하고, 다른 회로는 1에 해당하는 가지들을 절단하여 두 회로의 출력을 비교함으로써 디코딩한다. 이 때, 두 회로 출력 값의 차이가 작을 경우에는 하드웨어 구현시의 mismatching 때문에 디코딩 에러가 발생할 수 있다. 본 논문에서는 입력 심볼 에러 값들을 증폭함으로서 큰 경로 에러 값들은 saturation시키는 대신, 작은 경로 에러 값들 간에는 구별 성을 키움으로써 결과적으로 0 혹은 1 간의 구별 마진이 커지게 하는 방법을 제안하였다. 회로의 디코딩 성능 개선효과를 보이기 위해 시뮬레이션 결과를 제시하였다.

Keywords

References

  1. M. H. Shakiba, D. A. johns, and K. W. Martin, 'Bicmos circuits for analog viterbi decoders,' IEEE trans. on circuits and system-II, Analog and Digital Signal processin, pp.1527-1537, vol.45, no.12, Dec.1998 https://doi.org/10.1109/82.746664
  2. Jane Maunu, Mika laiho and Ari paassio, 'A differential architecture for an online analog viterbi decoder, IEEE Trans. on circuit and system-I,regular paper, vol.55, no.4, pp.1133-1140, May2008 https://doi.org/10.1109/TCSI.2008.916546
  3. F. Dolivo, 'Signal processing for high-density magnetic recording,' Proc. of VLSI and computer peripherals, pp.1.91-1.96,1989 https://doi.org/10.1109/CMPEUR.1989.93353
  4. H. Kobayashi and D. T. Tang, 'Application of partial response channel coding to magnetic recording system,' IBM journal of research and development. pp.368-375,1970 https://doi.org/10.1147/rd.144.0368
  5. A.J. Viterbi, 'Error bounds for convolution codes and asymptotically optimum decoding algoritham' IEEETrans.Oninformationtheory,vol.13,pp.260-269.1967 https://doi.org/10.1109/TIT.1967.1054010
  6. R.D. Ciderciyan, F. Dolvio, R. Hermann, W. Schoot, 'A PRML system for digital magnetic recording,' IEEE Trans. On selected area communication, vol.10, no.1,pp.38-56,1992 https://doi.org/10.1109/49.124468
  7. Sun-How Jiang and Feng-Hsiang Lo, 'PRML process of multilevel run length-limited modulation recording on optical disk,' IEEE Trans. On magnetism, vol.41, no.2, pp.1070-1072, Feb.2005 https://doi.org/10.1109/TMAG.2004.842015
  8. G. D. Forney, JR. 'The viterbi algorithm,' Proc. of the IEEE, vol.61, no.3, March.1973 https://doi.org/10.1109/PROC.1973.9030
  9. Hyongsuk Kim, Hongrak Son, Tamas Roska and Leon O. Chua, 'High performance viterbi decoder with circularly connected 2-D CNN unilateral cell array,' IEEE Trans. on circuit and system-I, vol.52, no.10, pp.2208-2218, Oct.2005 https://doi.org/10.1109/TCSI.2005.853263
  10. Hyunjung Kim, Hongrak Son, Jeonwon lee, In-cheol Kim and Hyongsuk Kim, 'Analog viterbi decoder for PRML using analog parallel processing circuits of the CNN,' 10th International workshop on Cellular neural networks and their application, Istanbul, Turkey, Aug.2006 https://doi.org/10.1109/CNNA.2006.341657
  11. P. R. Kinget, 'Device mismatch and tradeoffs in the design of analog circuits,' IEEE J. Solid-State Circuits, vol.40, no.6, pp.1212-1224, Jun.2005 https://doi.org/10.1109/JSSC.2005.848021
  12. P. G. Gulakand E. Shwedyk. 'VLSI structures for viterbi receivers: Part I - general theory and applications,' IEEE J. on Selected areas in comm., vol. 4, pp. 142-154, Jan. 1986 https://doi.org/10.1109/JSAC.1986.1146304
  13. Jens Sparso, Henrik N., Jorgenson,'An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures,' IEEE Jr. Solid-State Circuit, vol. SC-26. no. 2, pp. 90-96, Feb. 1991 https://doi.org/10.1109/4.68122
  14. Kai He and Gert Cauwenberghs, 'Integrated 64-state parallel analog Viterbi decoder,' Proceedings of ISCAS 2000, Geneva, Swiss, vol. IV, pp. 761-764 https://doi.org/10.1109/ISCAS.2000.858863
  15. M. Moerz, A. Schaefer, 'Analog decoders for high rate convolutional codes,' IWT 2001, Australia, pp. 128-130 https://doi.org/10.1109/ITW.2001.955160