1 |
J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. Dally, M. Horowitz, "A 14-mW 6.25Gb/s Transceiver in 90-nm CMOS", IEEE J. Solid-State Circuits, pp. 2745-2757, Dec. 2007.
|
2 |
K. Kaviani, A. Amirkhany, C. Huang, P. Le, W. Beyene, C. Madden, K. Saito, K. Sano, V. Murugan, K. Chang, and X. Yuan, "A 0.4-mW/Gb/s near-ground receiver front-end with replica transconductance termination calibration for a 16-Gb/s source-series terminated transceiver" IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 636-648, Mar. 2013
DOI
ScienceOn
|
3 |
Young-Hoon Song, Rui Bai, Kangmin Hu, Hae-Woong, Patrick Yin chiang, Samuel Palermo, "A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65nm CMOS" IEEE J. Solid-State Circuits, VOL.5 pp. 1276-1289, May. 2013.
|
4 |
K. Abugharbieh, S. Krishnan, J. Mohan, Varadarajan Devnath, and I. Duzevik, "An ultralow-power 10Gbits/s LVDS output driver," IEEE Trans, Circuits Syst. I, Reg.Papers, vol. 57, no 1, pp. 262-269, Jan. 2010.
DOI
ScienceOn
|
5 |
K. Kaviani et al. A 6.4-Gb/s near-ground single-ended transceiver for dual-rank dimm memory interface systems. In International Solid-State Circuits Conference, February 2013.
|
6 |
B. Nickolic, et al, "Sense-Amplifier based flip-flop," ISSCC Dig. Tech, Papers, pp. 282-283, Feb. 1999.
|
7 |
B. Leibowitz, R. Palmer, J. Poulton, Y. Frans, S. Li, J. Wilson, M. Bucher, A. Fuller, J. Eyles, M. Aleksic, T. Greer, N. Nguyen, "A 4.3 GB/s memory interface with power-efficient bandwidth scaling," IEEE J. Solid-State Circuits, pp. 889-898, Apr. 2010.
|