• 한국전기전자재료학회논문지
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• 제23권2호
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• pp.89-92
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• 2010

A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.387-391
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• 2011

A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.

• 제어로봇시스템학회논문지
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• 제6권2호
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• pp.121-126
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• 2000

In the fast sampling limit the delta operator model tends to the analog system model. This fundamental property of the delta operator model unifies continuous and discrete time control system. In this paper we study robust linear optimal model following servo system in the presence of disturbances and parameter perturbations. A technique to directly design the generalized differential operator based unified control system that covers both differential operator based continuous time and delta operator based discrete time case is presented. The quadratic criterion function for a linear system is used to design the robust unified servo control system The characteristics of the proposed servo system are analysed and simulated to verify the robustness.

• 대한전기학회논문지:전력기술부문A
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• 제48권6호
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• pp.747-752
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• 1999

In the fast sampling limit, the delta operator model tends to the analog system model. This fundamental property of the delta operator model unifies continuous and discrete time control system. In this paper, we study robust linear optimal model following servo system in the presence of disturbances and parameter perturbations. A technique to directly design the generalized differential operator based unified control system that convers both differential operator based continuous time and delta operator based discrete time case is presented. The quadratic criterion function for a linear system is used to design the robust unified servo control. The characteristics of the proposed servo system are analysed and simulated to verify the robustness.

• 전기학회논문지
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• 제57권6호
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권9호
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• pp.650-656
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• 2004

This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.

• 대한전자공학회논문지SD
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• 제41권9호
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• pp.107-114
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• 2004

본 논문에서는 DWA(Data Weighted Averaging) 방식의 sigma-delta 변조기에서 피드백 지연시간을 최적화 할 수 있는 DWA 구조의 블록도 및 타이밍도를 제안한다. 변조기 설계를 위하여 MATLAB 모델링으로 적분기의 최적 계수를 설정한 후 변조기의 비이상성을 고려하여 완전 차동 SC 적분기, 피드백 DAC, 9-레벨 양자화기, DWA를 설계하였다. 각 블록을 이용하여 실현된 3차 멀티비트 sigma-delta 변조기는 0.35㎛ CMOS 공정으로 칩으로 제작하였고, 동작 특성은 1.2Vp-p 825kHz의 입력 신호, 샘플링 주파수 52.8MHz에서 75dB의 SNR과 74dB의 DR을 가진다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.156-159
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• 2000

This paper presents a low-voltage, low-power $\Sigma$Δ modulator for audio applications. It use a simple second-order fully-differential switched-capacitor structure with a sampling frequency of 12.5 MHz and oversampling ratio of 256. It operates from a single 1.5V Bower supply and dissipates 2 ㎽. Extensive simulations using 0.25 ${\mu}{\textrm}{m}$ CMOS Process parameters show that it achieves 96㏈ peak SNDR in a 22 KHz bandwidth.

• Journal of Electrical Engineering and Technology
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• 제7권2호
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• 대한전자공학회논문지
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• 제21권3호
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• pp.73-83
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• 1984

본 논문에서는 embedded ADPCM, embedded ABM 및 delayed decision 방식을 사용한 system이 실제 음성을 부호화할 때 그 성능을 연구하였다. Embedded ADPCM과 ADM 부호화기는 종래의 ADPCM과 ADM 부호화기를 개조함으로써 얻어졌다. Embedded ADPCM 부호화기는 기본적으로 Cummiskey에 의해 최초로 제안된 바 있는 ADPCM을 기초로 하고 있다. Embedded ADM system은 CVSD와 HCDM system을 개조하여 만들었다. 이들 embedded 부호화기 중에서 embedded HCDM의 성능이 다른 부호화기에 비하여 16kbits/s에서 64kbits/s의 넓은 범위의 전송률에 걸쳐 우수하다. Embedded ADPCM에 delayed decision 방식을 적용하면 모든 전송률에서 성능이 크게 향상된다. 그러나 16kHz로 sample되는 embedded ADM system에 있어서는 같은 수의 지연 sample을 가진 embedded ADPCM에서 만큼 크게 성능이 향상되지는 않음을 알아내었다.